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High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs
Junan Lee,Himchan Park,Bongsub Song,Kiwoon Kim,Jaeha Eom,Kyunghoon Kim,Jinwook Burm IEEE 2015 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.62 No.9
<P>This paper proposes a column-parallel two-step single-slope analog-to-digital converter (SS ADC) for high-frame-rate CMOS image sensors. The proposed two-step SS ADC circuit does not utilize an analog memory capacitor to store the value of the first ramp step. Instead, to handle problems such as the slope errors of the second ramp and the stored charge error from charge feed-through, it utilizes a very simple digital column circuit consisting of a coarse counter (coarse step counter) and a 4-to-16 decoder. The second ramp (fine ramp) slope has only one slope generator, regardless of the results of the first ramp decisions, to eliminate the slope mismatch between fine ramp slopes. A prototype sensor comprising 640 × 480 pixels was fabricated with a 0.13- μm CMOS process. The results of experiments conducted indicate that the proposed ADC can achieve a conversion time of 6.4 μs at a main clock frequency of 62.5 MHz, which is 10.2 times faster than the conventional SS ADC. The maximum frame rate of the proposed VGA CMOS Image Sensor (CIS) is 320 frames per second (fps). Further, the proposed circuit employs redundancy error correction logic to calibrate the error between the coarse and fine steps. The total power consumption is 72 mW from supply voltages of 2.8 V (analog) and 1.5 V (digital). The figure of merit (FoM) of the proposed VGA CMOS image sensor is 2.01 [e<SUP>-</SUP> nJ].</P>
High Frame Rate VGA CMOS Image Sensor using Three Step Single Slope Column-Parallel ADCs
Lee, Junan,Huang, Qiwei,Kim, Kiwoon,Kim, Kyunghoon,Burm, Jinwook The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.1
This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SS-ADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SS-ADC. The proposed three-step SS-ADC has a 12-bit resolution and 200 kS/s at 25 MHz clock frequency. The VGA CIS using three step SS-ADC has the maximum frame rate of 200 frames/s. The total power consumption is 76 mW with 3.3 V supply voltage without ramp generator buffer. A prototype chip was fabricated in a $0.13{\mu}m$ CMOS process.
High Frame Rate VGA CMOS Image Sensor using Three Step Single Slope Column-Parallel ADCs
Junan Lee,Qiwei Huang,Kiwoon Kim,Kyunghoon Kim,Jinwook Burm 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.1
This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SSADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SSADC. The proposed three-step SS-ADC has a 12-bit resolution and 200 kS/s at 25 ㎒ clock frequency. The VGA CIS using three step SS-ADC has the maximum frame rate of 200 frames/s. The total power consumption is 76 ㎽ with 3.3 V supply voltage without ramp generator buffer. A prototype chip was fabricated in a 0.13 μm CMOS process.
Improved Circuits for Single-photon Avalanche Photodiode Detectors
Kyunghoon Kim,Junan Lee,Bongsub Song,Jinwook Burm 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.6
A CMOS photo detection bias quenching circuit is developed to be used with single photon avalanche photodiodes (SPADs) operating in Geiger mode for the detection of weak optical signals. The proposed bias quenching circuits for the performance improvement reduce the circuit size as well as improve the performance of the quenching operation. They are fabricated in a 0.18-㎛ standard CMOS technology to verify the effectiveness of this technique with the chip area of only 300 ㎛², which is about 60 % of the previous reported circuit. Two types of proposed circuits with resistive and capacitive load demonstrated improved performance of reduced quenching time. With a commercial APD by HAMAMATSU, the dead time can be adjusted as small as 50 ㎱.
An Ultralow Power Time-Domain Temperature Sensor With Time-Domain Delta–Sigma TDC
Song, Wonjong,Lee, Junan,Cho, Nayeon,Burm, Jinwook IEEE 2017 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.64 No.10
<P>Without using bipolar transistors, serially connected inverter cells generate clock delay according to temperature. The delay is compared with a reference clock to estimate the temperature. The proposed time-to-digital converter (TDC) structure is using a time-domain delta-sigma (Delta Sigma) modulator. This type of TDC with Delta Sigma modulator can achieve higher resolution by increasing the oversampling ratio, with the advantages of low area and low power consumption. To increase the accuracy by producing true temperature-independent time delay, an external reference clock is utilized, instead of temperature-independent inverter cells, for robust operations. The measured temperature sensors demonstrated a minimum power consumption of 480 nW and a resolution under 0.1 degrees C. The 3 sigma error of the sensor is +/- 0.99 degrees C over -20 degrees C-80 degrees C temperature range from ten-sample measurement results. The chip area is 0.089 mm(2) using a Dongbu 0.18-mu m CMOS process. The conversion rate is 1.25 samples/s.</P>
Improved Circuits for Single-photon Avalanche Photodiode Detectors
Kim, Kyunghoon,Lee, Junan,Song, Bongsub,Burm, Jinwook The Institute of Electronics and Information Engin 2014 Journal of semiconductor technology and science Vol.14 No.6
A CMOS photo detection bias quenching circuit is developed to be used with single photon avalanche photodiodes (SPADs) operating in Geiger mode for the detection of weak optical signals. The proposed bias quenching circuits for the performance improvement reduce the circuit size as well as improve the performance of the quenching operation. They are fabricated in a $0.18-{\mu}m$ standard CMOS technology to verify the effectiveness of this technique with the chip area of only $300{\mu}m^2$, which is about 60 % of the previous reported circuit. Two types of proposed circuits with resistive and capacitive load demonstrated improved performance of reduced quenching time. With a commercial APD by HAMAMATSU, the dead time can be adjusted as small as 50 ns.
A 0.18-<tex> $\mu$</tex> m CMOS 10-Gb/s Dual-Mode 10-PAM Serial Link Transceiver
Bongsub Song,Kyunghoon Kim,Junan Lee,Jinwook Burm IEEE 2013 IEEE transactions on circuits and systems. a publi Vol.60 No.2
<P>A 0.18-μm CMOS 10-Gb/s serial link transceiver is presented. For the power-efficiency, the transceiver employs a dual-mode 10-level pulse amplitude modulation (10-PAM) technique enabling to transmit 4-bit per symbol. Since the operating frequency of the internal circuits is reduced by 4, the power dissipation of the transceiver is much reduced. In addition, compared with a standard 16-PAM technique, the dual-mode 10-PAM technique can reduce power dissipation by 62.5%. The transmitter including a pseudo random bit sequence (PRBS) generator, multiplexers, an encoder, and an output driver achieves 10-Gb/s data-rate with 235-mW power dissipation such that the figure of merit (FOM) of the transmitter part is 23.5 mW/(Gb/s). The receiver including a flash type analog-to-digital converter (ADC), a decoder, and output drivers achieves 10-Gb/s data-rate and 10<SUP>-12</SUP> BER with 190-mW power dissipation such that FOM of the receiver part is 19 mW/(Gb/s). The proposed 10-PAM transceiver was implemented in a 0.18-μm standard CMOS technology with 0.3 × 0.8-mm<SUP>2</SUP> active area.</P>