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Variable latency L1 data cache architecture design in multi-core processor under process variation
Joonho Kong 한국컴퓨터정보학회 2015 韓國컴퓨터情報學會論文誌 Vol.20 No.9
In this paper, we propose a new variable latency L1 data cache architecture for multi-core processors. Our proposed architecture extends the traditional variable latency cache to be geared toward the multi-core processors. We added a specialized data structure for recording the latency of the L1 data cache. Depending on the added latency to the L1 data cache, the value stored to the data structure is determined. It also tracks the remaining cycles of the L1 data cache which notifies data arrival to the reservation station in the core. As in the variable latency cache of the single-core architecture, our proposed architecture flexibly extends the cache access cycles considering process variation. The proposed cache architecture can reduce yield losses incurred by L1 cache access time failures to nearly 0%. Moreover, we quantitatively evaluate performance, power, energy consumption, power-delay product, and energy-delay product when increasing the number of cache access cycles.
A Locality-Aware Write Filter Cache for Energy Reduction of STTRAM-Based L1 Data Cache
Joonho Kong 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.1
Thanks to superior leakage energy efficiency compared to SRAM cells, STTRAM cells are considered as a promising alternative for a memory element in on-chip caches. However, the main disadvantage of STTRAM cells is high write energy and latency. In this paper, we propose a lowcost write filter (WF) cache which resides between the load/store queue and STTRAM-based L1 data cache. To maximize efficiency of the WF cache, the line allocation and access policies are optimized for reducing energy consumption of STTRAM-based L1 data cache. By efficiently filtering the write operations in the STTRAM-based L1 data cache, our proposed WF cache reduces energy consumption of the STTRAM-based L1 data cache by up to 43.0% compared to the case without the WF cache. In addition, thanks to the fast hit latency of the WF cache, it slightly improves performance by 0.2%.
Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations
Joonho Kong,Yan Pan,Ozdemir, S.,Mohan, A.,Memik, G.,Sung Woo Chung IEEE 2012 IEEE transactions on very large scale integration Vol.20 No.8
<P>Process variations cause large fluctuations in performance and power consumption in the manufactured chips, which eventually results in yield losses. In this paper, to mitigate access time failures and excessive leakage in caches, we propose a novel selective wordline boosting mechanism combined with SRAM cell arrays voltage lowering. Based on our evaluation, the proposed approach recovers up to 83.1% of the yield losses.</P>
On the Thermal Attack in Instruction Caches
Joonho Kong,John, Johnsy K,Eui-Young Chung,Sung Woo Chung,Jie Hu IEEE 2010 IEEE transactions on dependable and secure computi Vol.7 No.2
<P>The instruction cache has been recognized as one of the least hot units in microprocessors, which leaves the instruction cache largely ignored in on-chip thermal management. Consequently, thermal sensors are not allocated near the instruction cache. However, malicious codes can exploit the deficiency in this empirical design and heat up fine-grain localized hotspots in the instruction cache, which might lead to physical damages. In this paper, we show how instruction caches can be thermally attacked by malicious codes and how simple techniques can be utilized to protect instruction caches from the thermal attack.</P>
A Locality-Aware Write Filter Cache for Energy Reduction of STTRAM-Based L1 Data Cache
Kong, Joonho The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.1
Thanks to superior leakage energy efficiency compared to SRAM cells, STTRAM cells are considered as a promising alternative for a memory element in on-chip caches. However, the main disadvantage of STTRAM cells is high write energy and latency. In this paper, we propose a low-cost write filter (WF) cache which resides between the load/store queue and STTRAM-based L1 data cache. To maximize efficiency of the WF cache, the line allocation and access policies are optimized for reducing energy consumption of STTRAM-based L1 data cache. By efficiently filtering the write operations in the STTRAM-based L1 data cache, our proposed WF cache reduces energy consumption of the STTRAM-based L1 data cache by up to 43.0% compared to the case without the WF cache. In addition, thanks to the fast hit latency of the WF cache, it slightly improves performance by 0.2%.
An efficient trade-off between yield and energy for eDRAM caches under process variations
Kong, Joonho,Gong, Young-Ho Elsevier 2017 Microprocessors and microsystems Vol.55 No.-
<P><B>Abstract</B></P> <P>eDRAM cells have been considered as a promising alternative to conventional SRAM cells and already adopted in commercial processors. However, eDRAM cells need to be refreshed periodically, resulting in non-negligible energy and performance overhead. Moreover, under process variations, retention time of eDRAM cells exhibits non-uniform distributions. This phenomenon affects both manufacturing yield and eDRAM refresh burden. In this paper, we first analyze eDRAM module (cache) yield and retention time failure patterns under process variations. Based on our analysis, we disclose most of the failing cache lines have only one faulty cell and propose a cost-efficient technique to save those one-cell failing cache lines. Our technique maintains a one-cell failing line (OFL) buffer which manages the status of the one-cell failing cache lines. By effectively curing one-cell failing lines, our technique significantly improves manufacturing yield by up to 46.1% under the identical refresh intervals. In addition, our technique can be used to loosen refresh intervals with comparable yield. By using the loosened refresh intervals, our technique reduces energy per instruction and improves performance by up to 19.9% and 1.3%, respectively.</P>
Seo, Joonho,Kim, Sun Kwon,Kim, Young-sun,Choi, Kiwan,Kong, Dong Geon,Bang, Won-Chul IEEE 2014 IEEE Transactions on Biomedical Engineering Vol.61 No.11
<P>Ultrasound (US)-based thermal imaging is very sensitive to tissue motion, which is a major obstacle to apply US temperature monitoring to noninvasive thermal therapies of in vivo subjects. In this study, we aim to develop a motion compensation method for stable US thermal imaging in in vivo subjects. Based on the assumption that the major tissue motion is approximately periodic caused by respiration, we propose a motion compensation method for change in backscattered energy (CBE) with multiple reference frames. Among the reference frames, the most similar reference to the current frame is selected to subtract the respiratory-induced motions. Since exhaustive reference searching in all stored reference frames can impede real-time thermal imaging, we improve the reference searching by using a motion-mapped reference model. We tested our method in six tumor-bearing mice with high intensity focused ultrasound (HIFU) sonication in the tumor volume until the temperature had increased by 7°C. The proposed motion compensation was evaluated by root-meansquare-error (RMSE) analysis between the estimated temperature by CBE and the measured temperature by thermocouple. As a result, the mean±SD RMSE in the heating range was 1.1 ± 0.1°C with the proposed method, while the corresponding result without motion compensation was 4.3 ± 2.6°C. In addition, with the idea of motion-mapped reference frame, total processing time to produce a frame of thermal image was reduced in comparison with the exhaustive reference searching, which enabled the motioncompensated thermal imaging in 15 frames per second with 150 reference frames under 50% HIFU duty ratio.</P>