80 µW/MHz, 850 MHz Fault Tolerant Processor with Fault Monitor Systems

Han, Jinho,Kwon, Youngsu,Shin, Kyeongsun,Yoo, Hoi-Jun The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.5

The processor is becoming increasingly susceptible to transient faults with fluctuating voltage, widening operating temperature, and increasing clock frequency. Especially, processor, operating near threshold voltage for a low power, can expose to transient faults with the thin margin of process, voltage, and temperature. This paper presents a fault tolerant processor having on-chip fault monitor systems for processor core and cache, which detects faults and corrects faults, and a fault injector which injects faults for testing. The fault tolerant feature is analyzed by a fault injection and quantitative analysis complying with ISO26262 standard. As a result, the proposed work achieves $80{\mu}W/MHz$ energy efficiency, 850 MHz maximum frequency, 72% fault trap reduction, and 99.23% single point fault failure rate complying with ISO26262.

40-TFLOPS artificial intelligence processor with function-safe programmable many-cores for ISO26262 ASIL-D

Han, Jinho,Choi, Minseok,Kwon, Youngsu Electronics and Telecommunications Research Instit 2020 ETRI Journal Vol.42 No.4

The proposed AI processor architecture has high throughput for accelerating the neural network and reduces the external memory bandwidth required for processing the neural network. For achieving high throughput, the proposed super thread core (STC) includes 128 × 128 nano cores operating at the clock frequency of 1.2 GHz. The function-safe architecture is proposed for a fault-tolerance system such as an electronics system for autonomous cars. The general-purpose processor (GPP) core is integrated with STC for controlling the STC and processing the AI algorithm. It has a self-recovering cache and dynamic lockstep function. The function-safe design has proved the fault performance has ASIL D of ISO26262 standard fault tolerance levels. Therefore, the entire AI processor is fabricated via the 28-nm CMOS process as a prototype chip. Its peak computing performance is 40 TFLOPS at 1.2 GHz with the supply voltage of 1.1 V. The measured energy efficiency is 1.3 TOPS/W. A GPP for control with a function-safe design can have ISO26262 ASIL-D with the single-point fault-tolerance rate of 99.64%.

Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator

Jinho Han,Jaehyeok Yang,Hyeon-Min Bae IEEE 2012 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.59 No.6

<P>This brief presents a theoretical analysis of the stochastic reference clock generator (SRCG), which creates a clock like periodic signal from a random nonreturn-to-zero data sequence. The output of the SRCG can be utilized as a reference clock for frequency acquisition in dual-loop clock-and-data recovery circuits. A frequency-locked loop (FLL) subsequent to the SRCG guides the voltage-controlled oscillator frequency into the pull-in range of the phase-locked loop while suppressing the high-frequency phase noise of the SRCG. The phase noise and frequency offset of the SRCG-FLL pair are analyzed. The validity of the theoretical analysis is supported by results taken from a test chip.</P>

80 μW/MHz, 850 MHz Fault Tolerant Processor with Fault Monitor Systems

Jinho Han,Youngsu Kwon,Kyeongsun Shin,Hoi-Jun Yoo 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.5

The processor is becoming increasingly susceptible to transient faults with fluctuating voltage, widening operating temperature, and increasing clock frequency. Especially, processor, operating near threshold voltage for a low power, can expose to transient faults with the thin margin of process, voltage, and temperature. This paper presents a fault tolerant processor having on-chip fault monitor systems for processor core and cache, which detects faults and corrects faults, and a fault injector which injects faults for testing. The fault tolerant feature is analyzed by a fault injection and quantitative analysis complying with ISO26262 standard. As a result, the proposed work achieves 80 μW/MHz energy efficiency, 850 MHz maximum frequency, 72% fault trap reduction, and 99.23% single point fault failure rate complying with ISO26262.

INTERNATIONAL COLLABORATION FOR SILICON CARBIDE MIRROR POLISHING AND DEVELOPMENT

HAN, JEONG-YEOL,CHO, MYUNG,POCZULP, GARY,NAH, JAKYUNG,SEO, HYUN-JOO,KIM, KYUNG-HWAN,TAHK, KYUNG-MO,KIM, DONG-KYUN,KIM, JINHO,SEO, MINHO,LEE, JONGGUN,HAN, SUNG-YEOP The Korean Astronomical Society 2015 天文學論叢 Vol.30 No.2

For research and development of Silicon Carbide (SiC) mirrors, the Korea Astronomy and Space Science Institute (KASI) and National Optical Astronomy Observatory (NOAO) have agreed to cooperate and share on polishing and measuring facilities, experience and human resources for two years (2014-2015). The main goals of the SiC mirror polishing are to achieve optical surface figures of less than 20 nm rms and optical surface roughness of less than 2 nm rms. In addition, Green Optics Co., Ltd (GO) has been interested in the SiC polishing and joined the partnership with KASI. KASI will be involved in the development of the SiC polishing and the optical surface measurement using three different kinds of SiC materials and manufacturing processes (POCO$^{TM}$, CoorsTek$^{TM}$ and SSG$^{TM}$ corporations) provided by NOAO. GO will polish the SiC substrate within requirements. Additionally, the requirements of the optical surface imperfections are given as: less than 40 um scratch and 500 um dig. In this paper, we introduce the international collaboration and interim results for SiC mirror polishing and development.

0.6–2.7-Gb/s Referenceless Parallel CDR With a Stochastic Dispersion-Tolerant Frequency Acquisition Technique

Jinho Han,Hyosup Won,Hyeon-Min Bae IEEE 2014 IEEE transactions on very large scale integration Vol.22 No.6

<P>A 0.6-2.7-Gb/s phase-rotator-based four-channel digital clock and data recovery (CDR) IC featuring a low-power dispersion-tolerant referenceless frequency acquisition technique is presented. A quasi-periodic reference clock signal extracted directly from a dispersed input signal is distributed to digitally controlled phase rotators in the CDR ICs for phase acquisition. A multiphase frequency acquisition scheme is employed for the reduction of the clock jitter. The measurement results show that the proposed design offers a lower frequency offset and clock noise floor under channel dispersion, as compared with conventional designs. The proposed four-channel digital CDR IC is fabricated in a 90-nm CMOS process. The figure of merit for a single channel is 8 mW/Gb/s such as a feedforward equalizer, a decision-feedback equalizer, and a referenceless CDR.</P>

알데바란 프로세서를 이용한 ISO26262 호환 자동차용 프로세서

한진호(Jinho Han),권영수(Youngsu Kwon) 대한전자공학회 2017 대한전자공학회 학술대회 Vol.2017 No.6

Advanced Driver Assistant System using vision processing is being equipped in automotive industries. Automotive processor , having the higher performance than one for engine and body control of vehicle is needed for the vision processing. So, We developed automotive processor with a fault tolerant feature and high performance for Automotive Vision Processor. First, We developed Aldebaran processor having 13 stage pipelines, dual-issue superscalar architecture, and caches. Second, We developed the fault tolerant feature in the cache and core of Aldebaran processor. We implemented the processor using FPGA and verified by running the Lane Departure Warning Algorithm.

니까노르 빠라의 반시에 나타난 생태주의 고찰 -빠라의 ‘정원’ 속 자연/인간 이분법의 해체-

한진호 ( Han Jinho ) 한국스페인어문학회 2023 스페인어문학 Vol.- No.109

With the publication of Ecopoemas (1982), a Chilean poet Nicanor Parra, whose fame lies in his antipoetry, inaugurated a new strategy for being ‘anti’ by initiating the ecopoetry. However, the poet’s view towards Nature and its relationship with human beings existed since his early works. This article attempts to provide the reader with ecocritical reading upon the antipoems of Parra based on two theories: the deep ecology of Arne Naess and the social ecology of Murray Bookchin. In Parra’s antipoems, jardín appears as a space for speakers to interact with Nature. In that Parra’s jardín is an artificially created nature within the city, this place is interpreted as ‘Second Nature’, a term which refers to the human society in social ecology. At the same time, the way how human beings mentally interact with Nature in jardín provides the model of ‘identification’, the process by which one attains an ecocentric way of thinking according to the theorists of deep ecology. With the convergence of two ecologies in jardín, Parra’s antipoems dissolve the strong antagonism between ecocentrism and anthropocentrism.

뇌과학 연구 성과를 반영한 교육과정 개발 연구

한진호 ( Jinho Han ),홍후조 ( Hoojo Hong ) 한국교육과정학회 2021 교육과정연구 Vol.39 No.3

본 연구는 오늘날 진일보를 거듭하는 신경과학기술의 수혜로 규명된 뇌 관련 지식을 활용하여, 교육과정을 개발하는 데 적용될만한 원리나 그 시사점을 도출하는데 목적을 두었다. 이를 위해 먼저 교육학에 적용될 수 있는 뇌의 주요 특성을 ‘가소성, 층위 포위성, 다양성, 사회성, 통합성’의 5가지로 정리하고, 문헌연구를 토대로 뇌기반 교육과정 개발 단계별 지침을 ‘교육목표 수립, 교육내용 선정, 교육내용 조직, 교육평가, 잠재적 교육과정’ 등 5개 영역의 틀로 총 84개의 항목을 개발하여 제시하였다. 이후 뇌과학에 대한 연구를 수행한 교육학자 25명을 패널로 구성하여 이들을 통한 내용타당도비율(CVR) 검증을 거쳐 2개 항목을 제외하고 최종 82개 항목을 교육과정 개발에 유관한 것으로 추출하였다. 또한 중요도-수행도 분석(IPA) 기법을 활용하여 항목별로 교육적 필요성의 우선순위에 대한 의사결정 토대를 구축하였으며, 중요성에도 불구하고 잘못 실행되거나 실행되지 않는 항목 23개를 중심으로 교육과정 실행지침 부분에 이들을 반영할 필요를 권고하였다. 그리고 이것이 장차 교육과정기준 문서의 개발에 줄 수 있는 시사점으로, ① 개별 학생의 독특한 뇌의 특성 존중, ② 역량을 뇌의 관점에서 해석, ③ 이성 뇌의 활성화를 위한 환경 조성으로서 안전 및 정서 함양 강조, ④이성 뇌의 효율적인 활용 강조, ⑤ 잠재적 교육과정에 대한 가이드라인 제시, ⑥ 뇌(신경)기반 문제행동 개선을 위한 학교와 전문기관의 협업 등을 논하였다. 본 연구는 학생들의 뇌 작동원리와 학습기제에 적합한 교육과정 계획 및 운영의 관점을 강조하며, 뇌기반 교육연구를 교육과정의 관점에서 재해석하고 종합하여 교육과정 개발과 교육활동 수행에 구체적이고 풍부한 지침을 제공하였다는 면에서 의의를 갖는다. The purpose of this study was to elicit the principles or implications applicable to the curriculum development by using the brain-related knowledge. For this first, the major features of brain which can be applied to a study of education were classified into brain plasticity, enveloping of layer, variety, sociality, and integrity. From a literature review, this study developed and presented total 84 items of guidelines in each stage of developing the brain-based curriculum through the five-domain frame: establishment of educational goals, selection of educational contents, organization of educational contents, educational evaluation, and latent curriculum. After going through the verification of CVR by 25 panels composed of educationalist who tries to link brain science research to education, this study finally extracted total 82 items related to the curriculum development. Also, using the IPA technique, established the decision-making foundation regarding the priority of educational necessity in each item. And as the implications for the curriculum standards development in the future, this study discussed ① the honor for unique brain characteristics of each individual student, ② the interpretation of competency in the perspective of brain, ③ the emphasis of safety and cultivating the emotion as an environment for the activation of rational brain, ④ the emphasis of efficient use of rational brain, ⑤ the presentation of guidelines for latent curriculum, and ⑥ the collaboration between school and specialized institution for the improvement of brain(nerve)-based problem behaviors. The significance of this study is to provide the concrete and abundant guidelines for the curriculum development and the performance of educational activities by emphasizing the perspective of planning and operating the curriculum suitable for the brain operation principles and learning mechanism of students, and then reinterpreting and putting together the brain-based education researches in the perspective of curriculum.

Single-Cell Isolation of Circulating Tumor Cells from Whole Blood by Lateral Magnetophoretic Microseparation and Microfluidic Dispensing

Kim, Jinho,Cho, Hyungseok,Han, Song-I,Han, Ki-Ho American Chemical Society 2016 ANALYTICAL CHEMISTRY - Vol.88 No.9

<P>This paper introduces a single-cell isolation technology for circulating tumor cells (CTCs) using a microfluidic device (the 'SIM-Chip'). The SIM-Chip comprises a lateral magnetophoretic microseparator and a micro dispenser as a two-step cascade platform. First, CTCs were enriched from whole blood by the lateral magnetophoretic microseparator based on immunomagnetic nanobeads. Next, the enriched CTCs were electrically identified by single-cell impedance cytometer and isolated as single cells using the microshooter. Using 200 mu L of whole blood spiked with 50 MCF7 breast cancer cells, the analysis demonstrated that the single-cell isolation efficiency of the SIM-Chip was 82.4%, and the purity of the isolated MCF7 cells with respect to WBCs was 92.45%. The data also showed that the WBC depletion rate of the SIM-Chip was 2.5 x 10(5) (5.4-log). The recovery rates were around 99.78% for spiked MCF7 cells ranging in number from 10 to 90. The isolated single MCF7 cells were intact and could be used for subsequent downstream genetic assays, such as RT-PCR Single-cell culture evaluation of the proliferation of MCF7 cells isolated by the SIM-Chip showed that 84.1% of cells at least doubled in 5 days. Consequently, the SIM-Chip could be used for single-cell isolation of rare target cells from whole blood with high purity and recovery without cell damage.</P>