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A New Algorithm for the Allocation of Functional Units and Connections onto Multiplexed Data Paths
park, In Hag,Brien, Kevin O`,Jerraya, Ahmed Amine,Courtois, Bernard 대한전자공학회 1991 ICVC : International Conference on VLSI and CAD Vol.2 No.1
This paper describes a new algorithm that allocates both functional unity (FUs), stored in an external user defined library, and connections. Our algorithm can generate several different structures by trading-off the costs of FUs and connections. This characteristic helps find a solution best fit to target architecture, because different target architectures demand different trade-offs. This algorithm is implemented in our data path synthesis system, called AMICAL, which facilitates the automatic, interactive or manual generation of microprocessor type data paths. The results obtained by this algorithm compare favorably with similar methods in the literature.
A Recursive High Level Synthesis System
Wang,J. C.,Teruya,M. Y.,Neto,J. V. Vale,Strum,M.,Jerraya,A. A. 대한전자공학회 1997 ICVC : International Conference on VLSI and CAD Vol.5 No.1
A hierarchical high level synthesis (HHLS) system, such as AMICAL, allows the obtaining of an architecture for a circuit from its behavioral description, written as a hierarchy of procedures and function calls, proper of large circuits. When specific modules are synthesized and reused as basic hardware modules in another HLS session, the resulting architecture may be inefficient due to operations overlap among the allocated hardware modules. This paper presents the structure of a CAD system that treats this problem by generating new hardware modules through a set of transformations to be applied to existing modules in an original library. We call the procedure of generating and reusing these new modules recursive high level syntheses (RHLS) which leads to a more efficient architecture. We propose a cost function that evaluates the quality of each architecture, taking into account area and time, and we present criteria to select the most promising transformation. The methodology is applied to a motor controller example (PID), showing its feasibility.