http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections
Jeong, Gyu-Seob,Hwang, Jeongho,Choi, Hong-Seok,Do, Hyungrok,Koh, Daehyun,Yun, Daeyoung,Lee, Jinhyung,Park, Kwanseo,Ko, Han-Gon,Lee, Kwangho,Joo, Jiho,Kim, Gyungock,Jeong, Deog-Kyoon IEEE 2018 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.65 No.10
<P>This brief presents a clocked pluggable optics suitable for high-density data center interconnections. The proposed architecture performs a SERDES function at the module side by exploiting a forwarded clock from the ASIC. Due to the relaxed channel loss of the ASIC-to-module interface, the use of power-hungry equalizers can be avoided. Based on an 850-nm multi-mode fiber interface, a 25-Gb/s link operation is demonstrated. A vertical-cavity surface-emitting laser-based transmitter outputs an optical modulation power of 0.6 mW. The optical receiver sensitivity is measured to be −7.5 dBm at 21.2 Gb/s with an optical excitation, and <TEX>$120~{\mu }\text{A}_{\text{pp}}$</TEX> at 25 Gb/s with an electrical excitation. The jitter tracking capability of the implemented clock and data recovery is evaluated in the presence of ±100-ppm frequency offsets and the measured jitter tolerance complies with the 100 GbE specification well. The optical transceiver is implemented in 65-nm CMOS technology and consumes 281 mW at 25 Gb/s, corresponding to the energy efficiency of 11.2 pJ/b.</P>
긴 명령어 워드 (Very Long Instruction Word) 를 가지는 마이크로 프로세서의 기술 동향
정덕균,문용 대한전자공학회 1995 CAD 및 VLSI 설계연구회지 Vol.4 No.1
In this paper, we present a basic concept, history, problem and the future of VLIW microprocessors. VLIW microprocessors rely on software rather than hardware for handling the complexity of parallelism. Hardware for VLIW architecture provides a simple instruction set processor for an optimizing compiler to utilize instruction level parallelism(ILP). We show examples of VLIW architectures and compiler techniques including scheduling algorithms. VLIW microprocessors are expected to be in the mainstream of high performance microprocessors because of its shift in better trade-off points between hardware and software.
A 0.25-<tex> $\mu$</tex>m CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture
Jeong, Hoesam,Yoo, Byoung-Joo,Han, Cheolkyu,Lee, Sang-Yoon,Lee, Kang-Yoon,Kim, Suhwan,Jeong, Deog-Kyoon,Kim, Wonchan IEEE 2007 IEEE journal of solid-state circuits Vol.42 No.6
<P> We present a 1.9-GHz Personal Handy-phone System (PHS) transceiver, fully integrated and fabricated in 0.25-<TEX>$\mu$</TEX> m CMOS technology. The receiver is based on a 150-kHz low-IF architecture and meets the fast channel switching and DC-offset cancellation requirements of PHS. It includes a low-noise amplifier (LNA), a downconversion mixer, a complex filter, and a programmable gain amplifier. A fractional-<B><I>N</I></B> frequency synthesizer achieves seamless handover with a 25 <TEX>$\mu$</TEX>s channel switching time and a phase noise of -121 dBc/Hz at a 600-kHz offset frequency, with compliant ACS performance. The receiver provides <TEX>${-}$</TEX>105 dBm sensitivity and 55 dBc ACS at a 600-kHz frequency offset. The transmitter is based on the direct modulation architecture and consists of an upconversion mixer and a pre-driver stage. The gain of the pre-driver is digitally controllable to suit any type of commercial power amplifier. The transmitter shows a 3% EVM and a 65 dBc ACPR at a 600-kHz offset frequency. The whole transceiver occupies 15.2 mm<TEX>$^{2}$</TEX> and dissipates 70 mA in RX and 44 mA in TX, with a 2.8-V supply. </P>
Jeong, Gyu-Seob,Kim, Wooseok,Park, Jaejin,Kim, Taeik,Park, Hojin,Jeong, Deog-Kyoon IEEE 2017 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.64 No.6
<P>This brief illustrates the design of an inductorless high-speed clock generator. Compared to inductance-capacitance (LC) oscillators, ring oscillators are used in order to achieve a wide frequency-tuning range with a small chip area. By employing a cascaded phase-locked loop (PLL) architecture, the phase noise of the oscillator can be effectively suppressed. The first PLL is implemented with high-voltage devices under 1.8-V supply to provide a clean reference for the second PLL. The second PLL consists of only low-voltage devices, with a supply voltage of 0.9 V for high-speed operation. Following the second PLL, a clock doubler multiplies the PLL output clock by a factor of 2, which avoids power-consuming high-frequency clock dividers. In order to minimize any mismatch effects, special layout techniques are employed for the second voltage-controlled oscillator and the clock doubler. The prototype chip was fabricated in 28-nm complementary metal oxide semiconductor (CMOS) technology, and it occupies an active area of only 0.015 mm(2). The proposed PLL achieves a maximum output frequency of 32 GHz and consumes a total power of 30 mW, exhibiting a power efficiency of 0.9 mW/GHz.</P>
A Fully Integrated 0.13- <tex> $\mu$</tex>m CMOS 40-Gb/s Serial Link Transceiver
Kim, Jeong-Kyoum,Kim, Jaeha,Kim, Gyudong,Jeong, Deog-Kyoon IEEE 2009 IEEE journal of solid-state circuits Vol.44 No.5
<P> A fully integrated 40-Gb/s transceiver fabricated in a 0.13-<TEX>$\mu$</TEX>m CMOS technology is presented. The receiver operates at a 20-GHz clock performing half-rate clock and data recovery. Despite the low <TEX>${\rm f}_{\rm T}$</TEX> of 70 GHz, the input sampler achieves 10-mV sensitivity using pulsed latches and inductive-peaking techniques. In order to minimize the feedback latency in the bang-bang controlled CDR loop, the proportional control is directly applied to the VCO, bypassing the charge pump and the loop filter. In addition, the phase detection logic operates at 20 GHz, eliminating the need for the deserializers for the early/late timing signals. The four clock phases for the half-rate CDR are generated by a quadrature LC-VCO with microstrip resonators. A linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening by 20% while operating at 39 Gb/s. The prototype transceiver occupies 3.4<TEX>$\, \times \,$</TEX>2.9 mm<TEX>$^{2}$</TEX> with power dissipation of 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 2<TEX>$^{15}-1$</TEX> PRBS data is 1.85 <TEX>${\rm ps}_{\rm rms}$</TEX> over a WB-PBGA package, an 8-mm PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable. The recovered divided-by-16 clock jitter is 1.77 <TEX>${\rm ps}_{\rm rms}$</TEX> and the measured BER of the transceiver is less than <TEX>$10^{- 14}$</TEX> . </P>