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Independent Double-Gate Fin SONOS Flash Memory Fabricated With Sidewall Spacer Patterning
Jang-Gn Yun,Yoon Kim,Il Han Park,Jung Hoon Lee,Daewoong Kang,Myoungrack Lee,Hyungcheol Shin,Jong Duk Lee,Byung-Gook Park IEEE 2009 IEEE transactions on electron devices Vol.56 No.8
<P>Fin silicon-oxide-nitride-oxide-semiconductor (SONOS) flash memories having independent double gates are fabricated and characterized. This device has two sidewall gates sharing one Si fin. To achieve narrow Si fin width over the photolithography limitation, sidewall spacer patterning is adopted. Specific fabrication processes for the fin SONOS flash memory having independent double gates are described. Electrical properties related to the opposite gate dependence are characterized. Measurement results of the paired cell interference are delivered.</P>
A 2-Bit Recessed Channel Nonvolatile Memory Device With a Lifted Charge-Trapping Node
Jang-Gn Yun,Il Han Park,Seongjae Cho,Jung Hoon Lee,Doo-Hyun Kim,Gil Sung Lee,Yoon Kim,Jong Duk Lee,Byung-Gook Park IEEE 2009 IEEE TRANSACTIONS ON NANOTECHNOLOGY Vol.8 No.1
<P>A novel 2-bit recessed channel nonvolatile memory device is proposed in this paper. Physically separated two charge-trapping nodes are lifted up to achieve large sensing margin in highly scaled memory devices. A successful 2-bit/cell operation with effective suppression of second bit effect is achieved by adopting the lifted charge-trapping node scheme. In addition, the effect of the source/drain junction depth on memory operation characteristics is investigated.</P>
Jang-Gn Yun,Il Han Park,박병국,Doo-Hyun Kim,Gil Sung Lee,Jong-Duk Lee,Jung Hoon Lee,조성재,김윤 한국물리학회 2007 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.51 No.III
The formation of Si-rich silicon nitride with low deposition rate has been investigated by using LPCVD for nanoscale non-volatile memory application. As the temperature increases, the deposition rate of silicon nitride increases dramatically. On the other hand, the pressure and gas flow ratio have little influence on the deposition rate. The refractive index tends to decrease as temperature decreases. At low temperature, Si-rich silicon nitride is formed under controlled gas flow ratio. By increasing the SiH$_2$Cl$_2$/NH$_3$ ratio, we can increase the refractive index of the silicon nitride. From the $I$-$V$ characteristics of MNOS devices, it is found that the silicon nitride with higher refractive index is more conductive because it contains more amorphous silicon. The $C$-$V$ curve hysteresis shows better memory characteristics in a device with Si-rich silicon nitride.
Characterization of 2-bit Recessed Channel Memory with Lifted Charge Trapping Node Scheme
Jang-Gn Yun,Il Han Park,Seongjae Cho,Jung Hoon Lee,Doo-Hyun Kim,Gil Sung Lee,Yoon Kim,Jong-Duk Lee,Byung-Gook Park 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
In this paper, characteristics of the 2-bit recessed channel memory with lifted charge storage nodes are investigated. The length between the charge storage nodes through channel, which is defined as the effective memory node length (Meff), is extended by lifting up them. The dependence of VTH window and short channel effect on the recessed depth is analyzed. Improvement of short channel effect is obtained because the recessed channel structure increases the effective channel length (Leff). This device shows highly scalable characteristics without suffering from the second bit effect.
Single-Crystalline Si STacked ARray (STAR) NAND Flash Memory
Jang-Gn Yun,Kim, Garam,Joung-Eob Lee,Yoon Kim,Won Bo Shim,Jong-Ho Lee,Hyungcheol Shin,Jong Duk Lee,Byung-Gook Park IEEE 2011 IEEE transactions on electron devices Vol.58 No.4
<P>In this paper, a 3-D NAND Flash memory array having multiple single-crystal Si nanowires is investigated. Device structure and fabrication process are described including the electrical isolation of stacked nanowires. Numerical simulation results focused on NAND Flash memory operation are delivered. Devices and array with stacked bit lines are fabricated, and memory characteristics such as program/erase select gate operation are measured. Array scheme is also discussed for the high-density bit-cost scalable 3-D stacked bit-line NAND Flash memory application.</P>
Jang-Gn Yun,Dae Woong Kwon,Sang Wan Kim,Jong-Ho Lee,Hyungcheol Shin,Jong Duk Lee,Byung-Gook Park 대한전자공학회 2010 ICEIC:International Conference on Electronics, Inf Vol.1 No.1
The three dimensional (3D) nanowire device having a body contact region is proposed. Effect of modulated gap width between body and source is simulated in a dumbbell-shaped 3D nanowire structure. For 3D stacked NAND flash memory array application, nanowire body-contacted common source line (CSL) structure is investigated. Specific design issue of ground select line (GSL) is also discussed.
Jang-Gn Yun,Se Hwan Park,Byung-Gook Park IEEE 2011 IEEE transactions on electron devices Vol.58 No.7
<P>A novel electrical layer-selection method in a bit-line stacked 3-D nand memory array is proposed. The stacked layers are selected by using multiple source select lines with erased cells in a layer. The operation scheme and simulation results for the electrical layer selection are discussed. An etch-through-spacer technique is developed to form a terraced body for a vertical contact process.</P>
2-bit Recessed Channel SONOS Memory with Vertical Split Gate Structure
윤장근(Jang-Gn Yun),박일한(Il Han Park),조성재(Seongjae Cho),이정훈(Jung Hoon Lee),김두현(Doo-Hyun Kim),이길성(Gil Sung Lee),김윤(Yoon Kim),이동화(Dong-Hua Lee),박세환(Se-Hwan Park),심원보(Won-Bo Sim),이종덕(Jong-Duk Lee),박병국(Byung- 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
A 2-bit recessed channel SONOS memory with vertical split gate structure is characterized through 2-dimensional numerical simulation. With a long effective channel length, this device is immune to the short channel effect [1]. The charge storage nodes are self-lifted from the bottom-side of channel and hence the second-bit effect is effectively suppressed. Furthermore, increased charge injection efficiency is expected because of the split gate structure. Therefore, enhanced programming characteristics with low second-bit effect can be achieved with simpler fabrication processes compared with the fanner methods [2], [3].