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A fully integrated 2.4-GHz CMOS RF transceiver for low-rate wireless sensor networks
Kwon, Ickjin,Song, Seong-Sik,Eo, Yunseong Wiley Subscription Services, Inc., A Wiley Company 2009 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS Vol.51 No.6
<P>This article describes a low-power and low-cost fully integrated 2.4 GHz IEEE 802.15.4 RF transceiver for low-rate wireless sensor networks. The RF transceiver adopts the single-IF direct-conversion architecture. For the high linearity, the RF receiver front end utilizes the current mirror amplifier as well as the transconductance linearization technique. The single-IF I/Q modulation transmitter is integrated with the current-mode analog baseband circuit and up-mixer using the current mirror amplifier. The frequency synthesizer based on an integer-N PLL topology offering 1.92 GHz differential and 0.48 GHz quadrature LO signals is also integrated on the RF transceiver. The fully integrated transceiver is fabricated in a 0.18-μm CMOS technology and its die size is 3.7 mm × 3.6 mm including ESD I/O pads. It achieves the −94 dBm receiver sensitivity, 8 dB receiver chain noise figure, and maximum transmitter output power of 1 dBm while drawing power consumption of 31 mW in the receive mode and 42 mW in the transmit mode with the 1.8 V supply. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1481–1487, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24349</P>
Kwon, Ickjin,Lee, Kwyro IEEE 2005 IEEE microwave and wireless components letters Vol.15 No.1
A low power 2.4-GHz complementary metal oxide semiconductor (CMOS) receiver front-end using highly linear mixer based on current amplification and mixing is reported. In the proposed mixer, linearity is greatly improved by using current mirror amplifier and transconductance linearization using multiple gated transistors. Single IF direct conversion receiver (DCR) architecture is used to achieve higher level of integration and to relax the problem of DCR. The fully integrated receiver front end is fabricated in 0.18-μm CMOS technology and HP3 of -9 dBm with a gain of 32 dB and noise figure of 6.5 dB are obtained at 8.8 mW power consumption.
A CMOS 6–10 GHz impulse radio UWB transmitter based on gated oscillator with switching pulse shaper
Park, Yangkyu,Kwon, Ickjin Elsevier 2018 Microelectronics journal Vol.77 No.-
<P><B>Abstract</B></P> <P>In an impulse radio ultra-wideband (IR-UWB) system for low-power location-aware sensor networks, the output pulses must meet the FCC spectral emission mask. In addition, to increase battery life, the IR-UWB transmitter must be energy efficient. In this paper, a CMOS ultra-wideband (UWB) transmitter designed using a 0.11-μm process is presented for 6–10 GHz applications. To reduce energy consumption, the transmitter adopts a gated voltage-controlled oscillator (VCO) that directly drives 50 Ω output impedance. A gated VCO that uses a trapezoidal pulse for on/off gating of the tail current source satisfies the spectrum mask without requiring an additional pulse shaping filter. The active energy consumption is 13.4 pJ/pulse at a pulse repeating frequency (PRF) of 40 MHz. The side-lobe rejection performance is more than 30 dB.</P>
Optimization of Low Power CMOS Baseband Analog Filter-Amplifier Chain for Direct Conversion Receiver
Minkyung Lee,Ickjin Kwon,Kwyro Lee 대한전자공학회 2004 Journal of semiconductor technology and science Vol.4 No.3
A low power CMOS receiver baseband analog circuit based on alternating filter and gain stages reported. For the given specifications of the baseband analog block, optimum allocation of the gain, IIP3 and NF of the each block was performed to minimize current consumption. The fully integrated receiver BBA chain is fabricated in 0.18 I'm CMOS technolog} and IIP3 of 30 dBm with a gain of 55 dB and noise figure of 31 dB are obtained at 4.86 mW power consumption.<br/>
Minyeon Cha,Ickjin Kwon 대한전자공학회 2011 Journal of semiconductor technology and science Vol.11 No.4
This paper describes a baseband analog (BBA) chain for wireless local area network (WLAN) applications. For the given specifications of the receiver BBA chain, the optimum allocation of the gain and filter rejection of each block in a BBA chain is achieved to maximize the SFDR. The fully integrated BBA chain is fabricated in 0.13 μm CMOS technology. An input-referred third-order intercept point (IIP3) of 22.9 dBm at a gain of 0.5 dB and an input-referred noise voltage (IRN) of 32.2 nV/√Hz at a gain of 63.3 dB are obtained. By optimizing the allocation of the gain and filter rejection using the proposed design methodology, an excellent SFDR performance of 63.9 dB is achieved with a power consumption of 12 mW.
CMOS impulse radio ultra-wideband Gaussian pulse generator with variable channel and bandwidth
Choi, Jamin,Kwon, Ickjin IET 2016 IET circuits, devices & systems Vol.10 No.2
<P>A Gaussian pulse generator for an ultra-wideband impulse radio transmitter is presented. The proposed generator is based on digital intensive circuits, and the centre frequency and bandwidth of a pulse are controlled by a digitally tunable delay circuit and pulse-width control circuit. The Gaussian pulse is obtained by a weighted summing amplifier that is controlled by a digital switching signal without an additional LC filter. The amplifier uses a Gaussian pulse shaper that has tunable weighting factors with bandwidth control. The energy consumption of the pulse generator is 37.4 pJ/pulse, and sidelobe rejection of 20 dB is achieved without a filter.</P>
오토트랜스포머를 이용한 RFID용 CMOS 송신 누설 신호 제거기
최인덕(Induck Choi),권익진(Ickjin Kwon) 한국전자파학회 2011 한국전자파학회논문지 Vol.22 No.8
본 논문에서는 UHF RFID 리더에서의 오토트랜스포머를 이용한 가변 송신 누설 신호 제거기를 제안하였다. 제안된 송신 누설 신호 제거기는 오토트랜스포머와 디지털 가변 캐패시터, 가변 저항, 보상 증폭기로 구성되었으며, 0.13 ㎛ 1-폴리 6-메탈 RF CMOS 공정을 사용하여 설계되었다. 시뮬레이션 결과, 제안된 구조는 송신단에서 수신단으로 신호가 전송될 때 55 ㏈ 이상의 송신 누설 신호 제거도를 보이며, 2.5 ㏈의 수신 삽입 손실을 갖는다. 송신 누설 신호 제거 회로는 825 ㎒에서 985 ㎒까지 디지털 주파수 조정이 가능하며, CMOS 공정으로 집적될 수 있다. In this paper, a tunable integrated transmitter leakage canceller based on an autotransformer for ultra-high-frequency (UHF) RFID readers is presented. The proposed TX leakage canceller consists of an autotransformer, a digital tuning capacitor, a voltage controlled tuning resistor, and a compensating amplifier, and it is designed using 0.13 ㎛ 1-poly 6-metal RF CMOS process. The simulation results show that the proposed structure has over 55 ㏈ rejection characteristic between a transmitter and a receiver and a 2.5 ㏈ of the RX insertion loss. The TX leakage canceller can be digitally tuned from 825 ㎒ to 985 ㎒ with the tuning capacitor and it can be fully integrated.