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민형철(Hyungcheol Min),이영곤(Younggon Lee),정해동(Haedong Jeong),박승태(Seungtae Park),이승철(Seungchul Lee) 한국소음진동공학회 2014 한국소음진동공학회 학술대회논문집 Vol.2014 No.10
In the process of MLCC manufacturing, MLCC stacking process is the key process of making high quality MLCC. Since MLCC is small components, the entire process of MLCC stacking process is minute and sensitive to micro errors. To prevent micro error, we suggest condition-based monitoring which quantifies error based on feature extraction and quantifying error method. As results, it has been shown that the suggested algorithm has effectiveness of condition based monitoring of MLCC stacker.
Min-Chul Sun,Hyun Woo Kim,Hyungjin Kim,Sang Wan Kim,Garam Kim,Jong-Ho Lee,Hyungcheol Shin,Byung-Gook Park 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.2
Control of threshold voltage (VT) by ground-plane (GP) technique for planar tunnel fieldeffect transistor (TFET) is studied for the first time using TCAD simulation method. Although GP technique appears to be similarly useful for the TFET as for the metal-oxide-semiconductor field-effect transistor (MOSFET), some unique behaviors such as the small controllability under weak ground doping and dependence on the dopant polarity are also observed. For VT-modulation larger than 100 mV, heavy ground doping over 1×1020 cm<SUP>-3</SUP> or back biasing scheme is preferred in case of TFETs. Polarity dependence is explained with a mechanism similar to the punch-through of MOSFETs. In spite of some minor differences, this result shows that both MOSFETs and TFETs can share common VT-control scheme when these devices are co-integrated.
A Digital TCXO with New Trimming Method
Hyungcheol Shin,Min-Kyu Jeon,Kyungmi Lee 에스케이텔레콤 (주) 2000 Telecommunications Review Vol.10 No.6
Recently, the demand for the stable temperature compensated crystal oscillators (TCXO) is increasing more and more and digital TCXOs (DTCXO) have been studied extensively because of their higher frequency accuracy and onechip implementation possibility. To develop a VLSI TCXO circuit, the DTCXO using capacitor array which is directly controlled by the digital code from the memory was proposed and how to organize the capacitor array has been studied. In this work, a new capacitor array scheme, called TACA (temperature compensated capacitor array) is proposed. It guarantees monotonicity and saves the silicon area at the same time. We also have developed TCXO, which can be used over wide range of frequency. The oscillator and the capacitor array were fabricated with a 0.5μm CMOS process. Complete digital trimming of the DTCXO with 0.2ppm trimming accuracy was achieved.
Sun, Min-Chul,Kim, Hyun Woo,Kim, Hyungjin,Kim, Sang Wan,Kim, Garam,Lee, Jong-Ho,Shin, Hyungcheol,Park, Byung-Gook The Institute of Electronics and Information Engin 2014 Journal of semiconductor technology and science Vol.14 No.2
Control of threshold voltage ($V_T$) by ground-plane (GP) technique for planar tunnel field-effect transistor (TFET) is studied for the first time using TCAD simulation method. Although GP technique appears to be similarly useful for the TFET as for the metal-oxide-semiconductor field-effect transistor (MOSFET), some unique behaviors such as the small controllability under weak ground doping and dependence on the dopant polarity are also observed. For $V_T$-modulation larger than 100 mV, heavy ground doping over $1{\times}10^{20}cm^{-3}$ or back biasing scheme is preferred in case of TFETs. Polarity dependence is explained with a mechanism similar to the punch-through of MOSFETs. In spite of some minor differences, this result shows that both MOSFETs and TFETs can share common $V_T$-control scheme when these devices are co-integrated.
Wavelet-like convolutional neural network structure for time-series data classification
Park, Seungtae,Jeong, Haedong,Min, Hyungcheol,Lee, Hojin,Lee, Seungchul Techno-Press 2018 Smart Structures and Systems, An International Jou Vol.22 No.2
Time-series data often contain one of the most valuable pieces of information in many fields including manufacturing. Because time-series data are relatively cheap to acquire, they (e.g., vibration signals) have become a crucial part of big data even in manufacturing shop floors. Recently, deep-learning models have shown state-of-art performance for analyzing big data because of their sophisticated structures and considerable computational power. Traditional models for a machinery-monitoring system have highly relied on features selected by human experts. In addition, the representational power of such models fails as the data distribution becomes complicated. On the other hand, deep-learning models automatically select highly abstracted features during the optimization process, and their representational power is better than that of traditional neural network models. However, the applicability of deep-learning models to the field of prognostics and health management (PHM) has not been well investigated yet. This study integrates the "residual fitting" mechanism inherently embedded in the wavelet transform into the convolutional neural network deep-learning structure. As a result, the architecture combines a signal smoother and classification procedures into a single model. Validation results from rotor vibration data demonstrate that our model outperforms all other off-the-shelf feature-based models.
Jeong-Hyong Yi,Hyungcheol Shin,Young-June Park,Hong Shick Min IEEE 2006 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABIL Vol.6 No.2
<P>In order to explain polarity-dependent device degradation observed in polysilicon-oxide-nitride-oxide-silicon (SONOS) transistors, a physics-based model is proposed. Comparing the trends in polarity-dependent electrical characteristics between two different gate dielectric structures of stacked oxide- nitride-oxide (ONO) and oxide alone (SiO<SUB>2</SUB>), it was demonstrated that the bimodal behavior observed in SONOS transistors is due to the stacked gate dielectric structure and that the device degradation is caused not by electrons but by holes. The proposed model is based on two models of the anode hole injection with maximum available hole energy E<SUB>max</SUB> and the hydrogen-released interface trap generation. It is shown that the device degradation Delta<SUP>*</SUP> in the stacked-ONO gate structure can be expressed by the total fluence of the hole Q<SUB>Ah</SUB> injected from the anode side as Delta<SUP>*</SUP>apQ<SUB>Ah</SUB> <SUP>0.25</SUP>. Utilizing a threshold voltage shift DeltaV<SUB>th</SUB> method, it was found that the gate conduction in SONOS transistors is governed by a specific tunneling process, which depends on the voltage drop V<SUB>OX </SUB> across the tunnel oxide. It is also shown that the gate conduction mechanism through the ONO stacks makes a smooth transition from one tunneling process to another depending on the relationship between the V<SUB>OX</SUB> and the tunneling barrier height of Phi<SUB>B</SUB></P>