Editorial

Hyunchol Shin,Hanho Lee 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.5

Source Degenerated Derivative Superposition Method for Linearizing RF FET Differential Amplifiers

Hyunchol Shin,Jongsik Kim,Namsoo Kim Professional Technical Group on Microwace Theory a 2015 IEEE Transactions on Microwave Theory and Techniqu Vol. No.

<P>The second-order interaction effect in a field-effect transistor (FET) differential amplifier is analyzed using the Volterra series analysis method. The analysis results reveal that the second-order interaction is inherent in the fully differential amplifier structure, and thus can never be cancelled out. In contrast, it is found that the second-order interaction is possibly cancelled out by adding source degeneration impedance in the pseudodifferential amplifier (PDA) structure. In addition, the second-order interaction cancellation condition in the PDA can be made more robust and wider over the input signal swing by adopting the derivative superposition (DS) method. By combining the second-order interaction cancellation technique and the DS technique, a differential source degenerated DS method is proposed for linearizing FET differential amplifiers. A 2-GHz differential amplifier based on the proposed structure is designed for a power amplifier driver in an RF transmitter. Fabricated in 0.13-μm CMOS, it operates from a 1.2-V supply with the power dissipation of 30.2 mW. Measurement results show that it achieves +30.4 dBm of peak output third-order intercept point, 43 dBc of C/I at 0-dBm output power, +9.7 dBm of output-referred P1dB, and +10.6 dB of power gain.</P>

UHF-Band TV Transmitter for TV White Space Video Streaming Applications

Hyunchol Shin,Hyukjun Oh 한국전자파학회JEES 2019 Journal of Electromagnetic Engineering and Science Vol.19 No.4

This paper presents a television (TV) transmitter for wireless video streaming applications in TV white space band. The TV transmitter is composed of a digital TV (DTV) signal generator and a UHF-band RF transmitter. Compared to a conventional high-IF heterodyne structure, the RF transmitter employs a zero-IF quadrature direct up-conversion architecture to minimize hardware overhead and complexity. The RF transmitter features I/Q mismatch compensation circuitry using 12-bit digital-to-analog converters to significantly improve LO and image suppressions. The DTV signal generator produces an 8-vestigial sideband (VSB) modulated digital baseband signal fully compliant with the Advanced Television System Committee (ATSC) DTV signal specifications. By employing the proposed TV transmitter and a commercial TV receiver, over-the-air, real-time, high-definition video streaming has been successfully demonstrated across all UHF-band TV channels between 14 and 69. This work shows that a portable hand-held TV transmitter can be a useful TVband device for wireless video streaming application in TV white space.

A 1.9–3.8 GHz <tex> $\Delta \Sigma$</tex> Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency

Shin, Jaewook,Shin, Hyunchol IEEE 2012 IEEE journal of solid-state circuits Vol.47 No.3

<P>A fast and high-precision all-digital automatic calibration circuit that is highly suited for <TEX>$\Delta \Sigma$</TEX> fractional-N synthesizers is designed to achieve a constant loop bandwidth and fast lock time over an octave tuning range. A high-speed frequency-to-digital converter (FDC) measures VCO frequency on-chip with a sub-<TEX>$f_{\rm REF}$</TEX> frequency resolution of <TEX>$f_{\rm REF}/k$</TEX> in a time period of <TEX>$k\cdot T_{\rm REF}$</TEX>. The on-chip detected VCO frequency is then used for calibrating the loop bandwidth and the VCO frequency. The loop bandwidth calibration circuit measures the VCO gain <TEX>$K_{\rm VCO}$</TEX> and uses it to precisely control the charge pump current, hence making the loop bandwidth constant. For the VCO frequency calibration, a minimum error code finding block significantly enhances the calibration accuracy by finding the truly closest code to the target frequency. Moreover, this method does not need to activate <TEX>$\Delta \Sigma$</TEX> modulator to achieve sub- <TEX>$f_{\rm REF}$</TEX> calibration resolution, which makes this technique much accurate and faster than the conventional ones. A 1.9–3.8 GHz <TEX>$\Delta \Sigma$</TEX> fractional-N synthesizer is implemented in 0.13 <TEX>$\mu$</TEX>m CMOS, demonstrating that the loop bandwidth calibration is completed in 1.1–6.0 <TEX>$\mu$</TEX>s with <TEX>${\pm}2\hbox{\%}$</TEX> accuracy and the VCO frequency calibration is completed in 1.225–4.025 <TEX>$\mu$</TEX>s, all across the entire octave tuning range.</P>

A CMOS Active-<i>RC</i> Low-Pass Filter With Simultaneously Tunable High- and Low-Cutoff Frequencies for IEEE 802.22 Applications

Hyunchol Shin,Youngcho Kim IEEE 2010 IEEE Transactions on Circuits and Systems II: Expr Vol.57 No.2

<P>An active resistor-capacitor low-pass filter with simultaneously programmable high-end and low-end cutoff frequencies is presented for IEEE 802.22 cognitive radio transmitter applications. Transfer function analysis shows that the integrator frequency of a dc offset cancellation block should be tuned inversely proportional to the open-loop gain to maintain the low-end cutoff frequency at a constant value. Realized in a 0.18- ¿m complementary metal-oxide-semiconductor, the low-end cutoff frequency is successfully tuned between 740 Hz and 10 kHz over the 30-dB gain variation. Measured results show that the gain is tuned from -16.3 to +13.9 dB, and the high-end cutoff frequency is tuned from 2.1 to 6.04 MHz, while drawing 4.5 mA from a 1.8-V supply.</P>

A Fast and High-Precision VCO Frequency Calibration Technique for Wideband <tex> $\Delta \Sigma $</tex> Fractional-N Frequency Synthesizers

Jaewook Shin,Hyunchol Shin IEEE 2010 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.57 No.7

<P>A VCO frequency calibration technique suitable for a wideband fractional-N PLL is presented. It provides a fast and high-precision search for an optimal discrete tuning curve of an LC VCO during the coarse tuning process in a fractional-N PLL. A high-speed frequency error detector (FED) converts the VCO frequency to a digital value and computes the exact frequency difference from a target frequency. A minimum error code finder finds an optimal code that is closest to the target frequency. Due to the pure digital domain operation, a ΔΣ modulator in PLL can be deactivated during the calibration process, which makes this technique fast and accurate especially for a ΔΣ fractional-N PLL. We achieve a single-bit calibration time of only kT<SUB>REF</SUB> for obtaining a frequency resolution of f<SUB>REF</SUB>/k, and compared to the conventional techniques, which is the best performance in terms of the calibration time versus resolution. Such fast VCO frequency calibration can greatly reduce the total lock time in a PLL. A 2.3-3.9 GHz fractional-N PLL employing the proposed calibration technique is implemented in 0.13 μm CMOS. Successful operation is verified through experimental results. The measured calibration time for a 6-bit capbank is 1.09 and 2.03 μs for a frequency resolution of 19.2 and 4.8 MHz, respectively.</P>

Multi-Gbit/s Digital I/O Interface Based on RF-Modulation and Capacitive Coupling

신현철(Hyunchol Shin) 한국전자파학회JEES 2004 Journal of Electromagnetic Engineering and Science Vol.4 No.2

We present a multi-Gbit/s digital I/O interface based on RF-modulation and capacitive-coupling over an impedance matched transmission line. The RF-interconnect(RFI) can greatly reduce the digital switching noise and eliminate the dc power dissipation over the channel. It also enables reduced signal amplitude(as low as 200 m V) with enhanced data rate and affordable circuit overhead. This paper addresses the system advantages and implementation issues of RFI. A prototype on-chip RFI transceiver is implemented in 0.18-μm CMOS. It demonstrates a maximum data rate of 2.2 Gbit/s via 10.5-GHz RF-modulation. The RFI can be very instrumental for future high-speed inter- and intra-ULSI data links.

A Delta-Sigma Fractional-N Frequency Synthesizer for Quad-Band Multi-Standard Mobile Broadcasting Tuners in 0.18-µm CMOS

Jaewook Shin,Jongsik Kim,Seungsoo Kim,Hyunchol Shin 대한전자공학회 2007 Journal of semiconductor technology and science Vol.7 No.4

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65 %. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in 0.18-μm CMOS, the PLL covers 154 ~ 303 MHz (VHF-III), 462 ~ 911 MHz (UHF), and 1441 ~ 1887 MHz (L1, L2) with two VCO’s while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

T-DMB/DAB/FM 수신기를 위한 광대역 델타시그마 분수분주형 주파수합성기

신재욱(Jaewook Shin),신현철(Hyunchol Shin) 大韓電子工學會 2010 電子工學會論文誌-SD (Semiconductor and devices) Vol.47 No.12

본 논문은 다중대역 송수신기 CMOS RFIC 단일 칩을 위한 광대역 델타시그마 분수분주형 주파수합성기에 관한 것이다. 광대역 VCO의 LC Tank에 6-bit Switched Capacitor Array Bank를 적용하여 2340∼3940 ㎒의 출력주파수 범위를 가지도록 하였으며, 위상동기 전 Capacitor Bank Code를 선택하기위한 VCO Frequency Calibration 회로는 전체 주파수대역에서 2 ㎲이하로 보정을 마치는 뛰어난 성능을 보여준다. 광대역 VCO로부터 T-DMB/DAB/FM Radio의 LO 신호를 생성하기 위해 선택 가능한 다중분주비 ÷2, ÷16, ÷32를 가지는 LO 신호 발생기는 L-Band (1173 ∼ 1973 ㎒), VHF-III (147 ∼ 246 ㎒), VFH-II (74 ∼ 123 ㎒)에서 I/Q신호를 생성한다. Integrated Phase Noise는 전체 대역에서 0.8 degree RMS이하로 측정되어 매우 낮은 위상잡음을 보여주었다. 또한, VCO Frequency Calibration 시간을 포함하는 주파수합성기의 전체 동기시간은 50 ㎲ 이하로 측정되었다. 이 광대역 델타시그마 분수분주형 주파수합성기는 0.13 ㎛ CMOS공정으로 제작되었으며, 1.2 V 전원전압에서 15.8 ㎃의 전류를 소모한다. This paper presents a wideband ΔΣ fractional-N frequency synthesizer for a multi-band single chip CMOS RFIC transceivers. A wideband VCO utilizes a 6-bit switched capacitor array bank for 2340∼3940 ㎒ frequency range. VCO frequency calibration circuit is designed for optimal capacitor bank code selection before phase locking process. It finishes the calibration process in 2 ㎲ over the whole frequency band. The LO generation block has selectable multiple division ratios of ÷2, ÷16, and ÷32 to generate LO I/Q signals for T-DMB/DAB/FM Radio systems in L-Band (1173 ∼ 1973 ㎒), VHF-III (147 ∼ 246 ㎒), VFH-II (74 ∼ 123 ㎒), respectively. The measured integrated phase noise is quite low as it is lower than 0.8 degree RMS over the whole frequency band. Total locking time of the ΔΣ frequency synthesizer including VCO frequency calibration time is less than 50 ㎲. The wideband ΔΣ fractional-N frequency synthesizer is fabricated in 0.13 ㎛ CMOS technology, and it consumes 15.8 ㎃ from 1.2 V DC supply.

USRP SDR 기반 JPEG 이미지 무선 전송 시스템 구현

신성진(Sungjin Shin),김승현(Seunghyeon Kim),손지훈(Jihoon sohn),신현철(Hyunchol Shin) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.6