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Hellestrand, Graham R. 대한전자공학회 1996 APCCAS:Asia Pacific Conference on Circuits And Sys Vol.1 No.1
The architecture of a CPU capable of both executing multithreaded user processes in a commercial multi-threaded operating system environment and rapidly (sub microsecond) responding to real-time events, such as those that arise in the processing and synchronization of audio-video-data streams constituting concurrent interactive multi-media sessions, is discussed in this paper. The rapid, often simple, responses of a CPU to prioritized requests requires careful design of the on chip caches and registers and management of tire hazards causing latencies in the CPU pipeline. The novel incorporation of a register cache its the CPU, its design, and the design of the instruction and data caches is described.
EFFICACY OF UNIFIED AND HETEROGENEOUS HARDWARE DESCRIPTION NOTATIONS
Kim,Kyung Sik,Hellestrand,Graham R.,Kanthamanon,Prasert,Lam,Alex C K 대한전자공학회 1995 ICVC : International Conference on VLSI and CAD Vol.4 No.1
This paper presents a technique to determine the possible parallelism between different control-structures in large hierarchical Control- and Data-Flow Graphs (CDFGs). The technique is based on a hierarchical bottom-up heuristic, which after resolving data-and control-dependencies between control-structures, parallelizes selected control-structures, subject to minimizing resource consumption. The purpose of the technique is to be able to predict resource consumption and estimate execution time for large CDFGs. The technique has been tested on several DCFGs with up to 1442 nodes. The results indicate, that the technique performs well; for one example it estimated a total speed-up of 44% at the expence of an estimated resource overhead of -0.1, and general the speed-up ranges from 8% to 44%.