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Converting Interfaces on Application-specific Network-on-chip
Kyuseung Han,Jae-Jin Lee,Woojoo Lee 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.4
As mobile systems are performing various functionality in the IoT (Internet of Things) era, network-on-chip (NoC) plays a pivotal role to support communication between the tens and in the future potentially hundreds of interacting modules in system-on-chips (SoCs). Owing to intensive research efforts more than a decade, NoCs are now widely adopted in various SoC designs. Especially, studies on application-specific NoCs (ASNoCs) that consider the heterogeneous nature of modern SoCs contribute a significant share to use of NoCs in actual SoCs, i.e., ASNoC connects non-uniform processing units, memory, and other intellectual properties (IPs) using flexible router positions and communication paths. Although it is not difficult to find the prior works on ASNoC synthesis and optimization, little research has addressed the issues how to convert different protocols and data widths to make a NoC compatible with various IPs. Thus, in this paper, we address important issues on ASNoC implementation to support and convert multiple interfaces. Based on the in-depth discussions, we finally introduce our FPGAproven full-custom ASNoC.
Library-based Mapping of Application to Reconfigurable Array Architecture
Kyuseung Han,Kiyoung Choi 대한전자공학회 2009 Journal of semiconductor technology and science Vol.9 No.4
Reconfigurable array architecture is recently attracting much attention. It is a flexible hardware architecture, which can dynamically change its configuration to execute various functions while maintainning high performance. However, pursuing flexibility and performance at the same time leads to complexity, thereby makes the mapping of applications a difficult process. There have been attempts to use compiler or high level synthesis techniques to solve the problem. In this paper, we propose yet another method, which uses libraries for the mapping to provide an abstracttion of the internal structure and at the same time to reduce the development time and efforts through the automated process. We have selected a JPEG decoder as an example to apply the proposed method. As a result, we obtained about 20% less performance compared to manual mapping but development time is dramatically reduced to less than 1%.
Converting Interfaces on Application-specific Network-on-chip
Han, Kyuseung,Lee, Jae-Jin,Lee, Woojoo The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.4
As mobile systems are performing various functionality in the IoT (Internet of Things) era, network-on-chip (NoC) plays a pivotal role to support communication between the tens and in the future potentially hundreds of interacting modules in system-on-chips (SoCs). Owing to intensive research efforts more than a decade, NoCs are now widely adopted in various SoC designs. Especially, studies on application-specific NoCs (ASNoCs) that consider the heterogeneous nature of modern SoCs contribute a significant share to use of NoCs in actual SoCs, i.e., ASNoC connects non-uniform processing units, memory, and other intellectual properties (IPs) using flexible router positions and communication paths. Although it is not difficult to find the prior works on ASNoC synthesis and optimization, little research has addressed the issues how to convert different protocols and data widths to make a NoC compatible with various IPs. Thus, in this paper, we address important issues on ASNoC implementation to support and convert multiple interfaces. Based on the in-depth discussions, we finally introduce our FPGA-proven full-custom ASNoC.
SIMD 기계에서 중첩된 조건문을 위한 조건 실행 방법
한규승(Kyuseung Han),유준희(Junhee Yoo),최기영(Kiyoung Choi) 대한전자공학회 2010 대한전자공학회 학술대회 Vol.2010 No.6
When designing processors, SIMD technique is a widely used, simple and effective method for gaining performance. However, since the processing units inside the SIMD unit need to perform the same operation, it is difficult to deal with complex control flows, thus limiting performance gain. To solve this problem, SIMD-based processors usually adopt predicated execution schemes. However, it cannot solve the problem fully, since general predicated execution schemes do not support nested-if structures. Although there is an existing solution to the problem, it requires additional instructions to be inserted, thereby incurs some performance overhead. To eliminate this overhead, we propose a new predicated execution scheme for supporting nested-if structure, which requires only negligible area overhead and no performance overhead.
TEI-power : Temperature Effect Inversion--Aware Dynamic Thermal Management
Lee, Woojoo,Han, Kyuseung,Wang, Yanzhi,Cui, Tiansong,Nazarian, Shahin,Pedram, Massoud Association for Computing Machinery 2017 Transactions on Design Automation of Electronic Sy Vol.22 No.3
<P>FinFETs have emerged as a promising replacement for planar CMOS devices in sub-20nm technology nodes. However, based on the temperature effect inversion (TEI) phenomenon observed in FinFET devices, the delay characteristics of FinFET circuits in sub-, near-, and superthreshold voltage regimes may be fundamentally different from those of CMOS circuits with nominal voltage operation. For example, FinFET circuits may run faster in higher temperatures. Therefore, the existing CMOS-based and TEI-unaware dynamic power and thermal management techniques would not be applicable. In this article, we present TEI-power, a dynamic voltage and frequency scaling-based dynamic thermal management technique that considers the TEI phenomenon and also the superlinear dependencies of power consumption components on the temperature and outlines a real-time trade-off between delay and power consumption as a function of the chip temperature to provide significant energy savings, with no performance penalty-namely, up to 42% energy savings for small circuits where the logic cell delay is dominant and up to 36% energy savings for larger circuits where the interconnect delay is considerable.</P>