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A 12 bit 750 kS/s 0.13 mW Dual-sampling SAR ADC
Hamed Abbasizadeh,Dong-Soo Lee,Sang-Sun Yoo,Joon-Tae Kim,Kang-Yoon Lee 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.6
A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in 0.18-μm CMOS technology and occupies 0.728 mm2. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.
A Sub 1 V New Bandgap Reference Circuit with PSRR of -120dB
Hamed Abbasizadeh,Behnam Samadpoor Rikan,Dong-Soo Lee,Kang-Yoon Lee 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6
A Bandgap circuit capable of generating a reference voltage of less than 1V with high PSRR, low process, supply voltage and temperature sensitivity is proposed. High PSRR achieved by means of an improved current mode regulator which isolates the bandgap voltage from the variations and the noise of the power supply. The proposed circuit is implemented in a 0.35μm CMOS technology. The BGR circuit occupies 0.024 mm² of die area and consumes 90μW from a 5V supply voltage at room temperature. Experimental results demonstrate that the PSRR of the voltage reference has achieved - 120dB at frequencies up to 1kHz and -58dB@1MHz. A temperature coefficient of 60 ppm/°C is obtained in the range of -40°C to 120°C.
Accurate Sub-1 V CMOS Bandgap Voltage Reference with PSRR of -118 dB
Abbasizadeh, Hamed,Cho, Sung-Hun,Yoo, Sang-Sun,Lee, Kang-Yoon The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.4
A low voltage high PSRR CMOS Bandgap circuit capable of generating a stable voltage of less than 1 V (0.8 V and 0.5 V) robust to Process, Voltage and Temperature (PVT) variations is proposed. The high PSRR of the circuit is guaranteed by a low-voltage current mode regulator at the central aspect of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage $V_{reg}$ for the BG core and Op-Amp rather than the VDD. These current mirrors reduce the impact of supply voltage variations. The proposed circuit is implemented in a $0.35{\mu}m$ CMOS technology. The BGR circuit occupies $0.024mm^2$ of the die area and consumes $200{\mu}W$ from a 5 V supply voltage at room temperature. Experimental results demonstrate that the PSRR of the voltage reference achieved -118 dB at frequencies up to 1 kHz and -55 dB at 1 MHz without additional circuits for the curvature compensation. A temperature coefficient of $60 ppm/^{\circ}C$ is obtained in the range of -40 to $120^{\circ}C$.
A 12 bit 750 kS/s 0.13 mW Dual-sampling SAR ADC
Abbasizadeh, Hamed,Lee, Dong-Soo,Yoo, Sang-Sun,Kim, Joon-Tae,Lee, Kang-Yoon The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.6
A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.
A Low-Voltage Low-Power Opamp-Less 8-bit 1-MS/s Pipelined ADC in 90-nm CMOS Technology
Abbasizadeh, Hamed,Rikan, Behnam Samadpoor,Lee, Dong-Soo,Hayder, Abbas Syed,Lee, Kang-Yoon The Institute of Electronics and Information Engin 2014 IEIE Transactions on Smart Processing & Computing Vol.3 No.6
This paper presents an 8-bit pipelined analog-to-digital converter. The supply voltage applied for comparators and other sub-blocks of the ADC were 0.7V and 0.5V, respectively. This low power ADC utilizes the capacitive charge pump technique combined with a source-follower and calibration to resolve the need for the opamp. The differential charge pump technique does not require any common mode feedback circuit. The entire structure of the ADC is based on fully dynamic circuits that enable the design of a very low power ADC. The ADC was designed to operate at 1MS/s in 90nm CMOS process, where simulated results using ADS2011 show the peak SNDR and SFDR of the ADC to be 47.8 dB (7.64 ENOB) and 59 dB respectively. The ADC consumes less than 1mW for all active dynamic and digital circuitries.
Accurate Sub-1 V CMOS Bandgap Voltage Reference with PSRR of -118 ㏈
Hamed Abbasizadeh,Sung-Hun Cho,Sang-Sun Yoo,Kang-Yoon Lee 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.4
A low voltage high PSRR CMOS Bandgap circuit capable of generating a stable voltage of less than 1 V (0.8 V and 0.5 V) robust to Process, Voltage and Temperature (PVT) variations is proposed. The high PSRR of the circuit is guaranteed by a low-voltage current mode regulator at the central aspect of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage V<SUP>reg</SUP> for the BG core and Op-Amp rather than the V<SUP>DD</SUP>. These current mirrors reduce the impact of supply voltage variations. The proposed circuit is implemented in a 0.35 ㎛ CMOS technology. The BGR circuit occupies 0.024 ㎟ of the die area and consumes 200 ㎼ from a 5 V supply voltage at room temperature. Experimental results demonstrate that the PSRR of the voltage reference achieved -118 ㏈ at frequencies up to 1 ㎑ and -55 ㏈ at 1 ㎒ without additional circuits for the curvature compensation. A temperature coefficient of 60 ppm/℃ is obtained in the range of -40 to 120℃.
An Inductive 2-D Position Detection IC With 99.8% Accuracy for Automotive EMR Gear Control System
Kim, SangYun,Abbasizadeh, Hamed,Ali, Imran,Kim, Hongjin,Cho, SungHun,Pu, YoungGun,Yoo, Sang-Sun,Lee, Minjae,Hwang, Keum Cheol,Yang, Youngoo,Lee, Kang-Yoon IEEE 2017 IEEE transactions on very large scale integration Vol.25 No.5
<P>In this paper, the analog front end (AFE) for an inductive position sensor in an automotive electromagnetic resonance gear control applications is presented. To improve the position detection accuracy, a coil driver with an automatic two-step impedance calibration is proposed which, despite the load variation, provides the desired driving capability by controlling the main driver size. Also, a time shared analog-todigital converter (ADC) is proposed to convert eight-phase signals while reducing the current consumption and area to 1/8 of the conventional structure. A relaxation oscillator with temperature compensation is proposed to generate a constant clock frequency in vehicle temperature conditions. This chip is fabricated using a 0.18-mu m CMOS process and the die area is 2 mm x 1.5 mm. The power consumption of the AFE is 23.1 mW from the supply voltage of 3.3 V to drive one transmitter (Tx) coil and eight receiver (Rx) coils. The measured position detection accuracy is greater than 99.8 %. The measurement of the Tx shows a driving capability higher than 35 mA with respect to the load change.</P>
Danial Khan,Hamed Abbasizadeh,Zaffar Hayat Nawaz Khan,이강윤 한국과학기술원 반도체설계교육센터 2017 IDEC Journal of Integrated Circuits and Systems Vol.3 No.3
This paper presents an ultra-low power RF-DC voltage multiplier using auxiliary transistors block to dynamically control the threshold voltage of the main chain transistors. The proposed scheme enhances the forward conduction current and reduces the reverse current by controlling the gate to source voltage of the main chain transistors. The proposed 5-stage scheme attains maximum post-layout simulated power conversion efficiency (PCE) of 33.3% at -16dBm input level and delivers 2.63 V output DC voltage to 1MΩ load. The proposed RF-DC voltage multiplier has been designed in a standard 180 nm CMOS technology.
Design of an efficient RF-DC voltage multiplier for RF Energy Harvesting Applications
Danial Khan,Hamed Abbasizadeh,Zaffar Hayat Nawaz Khan,Truong Thi Kim Nga,Sang Yun Kim,Ho Cheol Ryu,Kang Yoon Lee 대한전자공학회 2017 대한전자공학회 학술대회 Vol.2017 No.1
In this paper, a RF-DC voltage multiplier is presented to efficiently convert RF signals to DC voltages. The proposed circuit uses an internal threshold voltage cancellation (IVC) scheme with auxiliary block to reduce the threshold voltage of forward-biased transistors and minimizes the reverse leakage current of the reverse-biased by dynamically controlling the gate-source voltage of the transistors in the main rectification chain. The proposed circuit is designed in 0.18 um CMOS technology. A three-stage voltage multiplier results in a maximum power conversion efficiency (PCE) of 49.1% at input power level of 0 dBm and at frequency of 900 MHz. The proposed circuit produces an output voltage of 4.94 V at 50 KΩ load.