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A Custom Code Generation Technique for ASIPs from High-level Language
알람 삼술,최광석,Alam, S.M. Shamsul,Choi, Goangseog Korea Society of Digital Industry and Information 2015 디지털산업정보학회논문지 Vol.11 No.3
In this paper, we discuss a code generation technique for custom transport triggered architecture (TTA) from a high-level language structure. This methodology is implemented by using TTA-based Co-design Environment (TCE) tool. The results show how the scheduler exploits instruction level parallelism in the custom target architecture and source program. Thus, the scheduler generates parallel TTA instructions using lower cycle counts than the sequential scheduling algorithm. Moreover, we take Tensilica tool to make a comparison with TCE. Because of the efficiency of TTA, TCE takes less execution cycles compared to Tensilica configurations. Finally, this paper shows that it requires only 7 cycles to generate the parallel TTA instruction set for implementing Cyclic Redundancy Check (CRC) applications as an input design, and presents the code generation technique to move complexity from the processor software to hardware architecture. This method can be applicable lots of channel Codecs like CRC and source Codecs like High Efficiency Video Coding (HEVC).
A DPLL with a Modified Phase Frequency Detector to Reduce Lock Time
하산 타릭,최광석,Hasan, Md. Tariq,Choi, GoangSeog The Institute of Electronics and Information Engin 2013 전자공학회논문지 Vol.50 No.10
A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took $0.304{\mu}s$ to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of $2.144{\mu}s$ to lock with a maximum jitter of approximately 0.1245 ns. 130nm CMOS 공정 라이브러리를 이용하여 125MHz로 동작하는 새로운 위상 주파수 검출기 기반 DPLL을 설계하였다. 이 DPLL은 중간 주파수대 응용을 위해 지터와 록 시간을 줄이려고 전형적인 DPLL에 반전 에지 검출기를 포함하고 있다. XOR 기반 반전 에지 검출기들은 출력을 보다 빨리 변화시키기 위하여 기준 신호보다 빠른 전이를 얻는데 사용된다. HSPICE 시뮬 레이터는 모의실험을 위해 Cadence환경에서 사용되었다. 제안된 위상 주파수 검출기를 가진 DPLL의 성능은 종래의 위상 주 파수 검출기를 가진 것의 성능과 비교하였다. 종래의 PLL은 약 0.1245 ns의 최대 지터를 가지고 록 하는데 최소 $2.144{\mu}s$가 걸린 반면에, 제안한 검출기를 가진 PLL은 약 0.1142 ns의 최대 지터를 가지고 록 하는데 $0.304{\mu}s$가 걸린다.
Enhanced Belief Propagation Polar Decoder for Finite Lengths
이크발 샤질,최광석,Iqbal, Shajeel,Choi, Goangseog Korea Society of Digital Industry and Information 2015 디지털산업정보학회논문지 Vol.11 No.3
In this paper, we discuss the belief propagation decoding algorithm for polar codes. The performance of Polar codes for shorter lengths is not satisfactory. Motivated by this, we propose a novel technique to improve its performance at short lengths. We showed that the probability of messages passed along the factor graph of polar codes, can be increased by multiplying the current message of nodes with their previous message. This is like a feedback path in which the present signal is updated by multiplying with its previous signal. Thus the experimental results show that performance of belief propagation polar decoder can be improved using this proposed technique. Simulation results in binary-input additive white Gaussian noise channel (BI-AWGNC) show that the proposed belief propagation polar decoder can provide significant gain of 2 dB over the original belief propagation polar decoder with code rate 0.5 and code length 128 at the bit error rate (BER) of $10^{-4}$.
단일 및 다중 라이시안 페이딩 채널에서 M-PSK 변조기술에서의 BER 유도
S.M. Shamsul Alam,최광석(GoangSeog Choi) 大韓電子工學會 2012 電子工學會論文誌-TC (Telecommunications) Vol.49 No.4
무선통신에서 페이딩은 피할 수 없는 문제이다. 그러므로 전송신호에 있어서는 BER 형태의 오류개념이 도입된다. 다른 페이딩 채널들 상에서 이러한 오류들의 동작을 인식하는 것이 필요하다. Coherent MPSK의 평균 BER에 대한 수학적인 해법을 얻기 위해서 몇 가지 기법들을 제안한다. 본 논문에서, 느리고 평탄한 라이시안 페이딩 채널 상에 diversity의 영향도 또한 분석되어진다. 여기서, 변조 지표 값 M은 변화하고 이 변화의 효과들 또한 묘사되어진다. 다양한 diversity 값과 페이딩 파라미터에 따른 성능 곡선들은 믿을 수 있는 통신 시스템을 위하여 무선 채널을 설계하고 평가하는데 유용하다. In wireless communication system, fading is an unavoidable problem. Hence, errors in form of BER are introduced with the transmitted signal. It is necessary to recognize the behavior of these errors in different fading channels. To obtain the mathematical solution for the average bit error rate(BER) of coherent MPSK, some techniques are presented. In this paper, the impact of diversity is also analyzed over slow and flat Rician fading channel. In here, the value of modulation index, M is varied and the effects of its variation are also depicted. So, these performance curves with different diversity values and fading parameter are useful to design and evaluate the radio channel for faithful communication system.
Hardware Implementation of Time Skew Calibration Block for Time Interleaved ADC
칸 사데크 레자,최광석,Khan, Sadeque Reza,Choi, Goangseog Korea Society of Digital Industry and Information 2017 디지털산업정보학회논문지 Vol.13 No.3
This paper presents hardware implementation of background timing-skew calibration technique for time-interleaved analog-to-digital converters (TI ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by using pure digital Finite Impulse Response (FIR) delay filter. This paper includes hardware architecture of the system, main units and small sub-blocks along with control logic circuits. Moreover, timing diagrams of logic simulations using ModelSim are provided and discussed for further understanding about simulations. Simulation process in MATLAB and Verilog is also included and provided with basic settings need to be done. For hardware implementation it not practical to work with all samples. Hence, the simulation is conducted on 512 TI ADC output samples which are stored in the buffer simultaneously and the correction arithmetic is done on those samples according to the time skew algorithm. Through the simulated results, we verified the implemented hardware is working well.