Design and Analysis of a Wideband 15–35-GHz Quadrature Phase Shifter With Inductive Loading

Sah, Suman P.,Xinmin Yu,Deukhyoun Heo IEEE 2013 IEEE transactions on microwave theory and techniqu Vol.61 No.8

<P>A Ku-, K-, and Ka-band phase shifter for beamforming applications is presented in this paper. An analysis showing the effect of loading conditions on quadrature phase accuracy in a simple poly-phase filter is carried out. Based on the analysis, a novel quadrature phase shifter (QPS) with inductive load is proposed. Sign-selection and vector addition is performed in two stages to lower supply voltage. The proposed phase shifter is fabricated in a 0.18- μm SiGe BiCMOS process and occupies an area of 520 μm×370 μm. The proposed QPS has a maximum phase error of 6.38<SUP>°</SUP> over 15-35 GHz while maintaining an amplitude imbalance less than 2 dB. When combined into a 4-bit phase shifter, the root mean square (rms) gain error is less than 2.2 dB and the rms phase error is less than 13<SUP>°</SUP> over 15-35 GHz. The phase shifter thus achieves a full 360<SUP>°</SUP> phase-shift range with 22.5 <SUP>°</SUP> phase resolution. The total power consumption is 14 mA from a 1.8-V power supply. The phase shifter achieves an input P1dB of -6.25 dBm. The measured phase-shifting fractional bandwidth of 87% is the highest reported thus far in the literature for SiGe BiCMOS implementation.</P>

CMOS Startup Charge Pump With Body Bias and Backward Control for Energy Harvesting Step-Up Converters

Peng, Huan,Tang, Nghia,Yang, Youngoo,Heo, Deukhyoun IEEE 2014 IEEE Transactions on Circuits and Systems I: Regul Vol.61 No.6

<P>A new low voltage charge pump is developed to help start up a step-up converter in energy harvesting applications. The proposed charge pump is the first to utilize both backward control scheme and two branches of charge transfer switches (CTSs) to direct charge flow. The backward control scheme uses the internal boosted voltage to dynamically control the CTSs' gate, and the two branches utilize both NMOS and PMOS to implement their switching structure. The combination of backward control scheme and two-branch operation allows the CTSs to be completely turned on and off. Thus, the reverse charge sharing phenomenon and switching loss are significantly reduced, which effectively improves pumping efficiency. The last stage is specially designed to improve the charge pump's charge and capacitance drivability. Using subthreshold operation and body-bias technique, the charge pump and its clock generator can operate under a low voltage supply. The proposed charge pump circuit is designed in a standard 0.18 mu m CMOS process. It consists of 6 stages, each with a 24 pF pumping capacitor (total 288 pF pumping capacitance area). Under a 320 mV supply, the measured output voltage of the proposed charge pump can rise from 0 to 2.04 V within 0.1 milliseconds.</P>

On the Effects of Mismatch on Quadrature Accuracy in Tapped-Capacitor Load Independent Quadrature LC-Oscillators

Sah, Suman P.,Agarwal, Pawan,Deukhyoun Heo IEEE 2014 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.61 No.5

<P>This paper presents a study of quadrature phase error due to various systematic mismatches and loading effects on the oscillation frequency in a tapped-capacitor parallel coupled LC-tank oscillator. Vector based analysis is carried out to evaluate the general oscillating condition. Closed-form expressions for oscillation frequency and quadrature accuracy in the presence of loading are derived for the case of weak coupling. It is shown with rigorous analysis, for the first time, that the tapped-capacitor LC-tank oscillator exhibits oscillation frequency that is independent of loading conditions. The analysis clearly demonstrates that the effects of mismatch in tapped-capacitors on quadrature accuracy can be minimized by proper choice of coupling factor and shows that the error due to these tapped-capacitors is independent of the quality factor of the tank. Results from Spectre simulations are used to validate the analytical results.</P>

Zero-Power Feed-Forward Spur Cancelation for Supply-Regulated CMOS Ring PLLs

Agarwal, Pawan,Kim, Jong-Hoon,Pande, Partha Pratim,Heo, Deukhyoun Institute of Electrical and Electronics Engineers 2018 IEEE transactions on very large scale integration Vol.26 No.4

<P>A new reference-spur cancelation technique is presented for supply-regulated ring-oscillator-based integer-N phase-locked loops (PLLs). A passive <I>RC</I> filter is used to implement a feed-forward (FF) spur-coupling path to perform spur cancelation at the PLL control signal. The proposed technique achieves a simulated spur cancelation of about 22 dB at the first spur harmonic. The simulated postcancelation spur value is −79 dBc for an oscillator gain of 0.1 GHz/V and −46 dBc for an oscillator gain of 6 GHz/V. Spur cancelation is also robust against large process, voltage, and temperature variations in the gain and bandwidth of the FF path. A 1-GHz integer-N PLL prototype in a 65-nm CMOS process has a measured cancelation of 19.5 and 13 dB at the first and the second spur harmonic, respectively, with <TEX>$320~\mu \text{W}$</TEX> of total power consumption. The PLL prototype has an oscillator gain of 1.5 GHz/V, which results in a postcancelation spur of −53 dBc. The proposed zero-power technique is suitable for low-power PLLs as it achieves a large spur cancelation without requiring any additional power consumption or calibration.</P>

A CMOS Envelope Tracking Power Amplifier for LTE Mobile Applications

Junghyun Ham,Haeryun Jung,Hyungchul Kim,Wonseob Lim,Deukhyoun Heo,Youngoo Yang 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.2

This paper presents an envelope tracking power amplifier using a standard CMOS process for the 3GPP long-term evolution transmitters. An efficiency of the CMOS power amplifier for the modulated signals can be improved using a highly efficient and wideband CMOS bias modulator. The CMOS PA is based on a two-stage differential common-source structure for high gain and large voltage swing. The bias modulator is based on a hybrid buck converter which consists of a linear stage and a switching stage. The dynamic load condition according to the envelope signal level is taken into account for the bias modulator design. By applying the bias modulator to the power amplifier, an overall efficiency of 41.7 % was achieved at an output power of 24 dBm using the 16-QAM uplink LTE signal. It is 5.3 % points higher than that of the power amplifier alone at the same output power and linearity.

A CMOS Envelope Tracking Power Amplifier for LTE Mobile Applications

Ham, Junghyun,Jung, Haeryun,Kim, Hyungchul,Lim, Wonseob,Heo, Deukhyoun,Yang, Youngoo The Institute of Electronics and Information Engin 2014 Journal of semiconductor technology and science Vol.14 No.2

This paper presents an envelope tracking power amplifier using a standard CMOS process for the 3GPP long-term evolution transmitters. An efficiency of the CMOS power amplifier for the modulated signals can be improved using a highly efficient and wideband CMOS bias modulator. The CMOS PA is based on a two-stage differential common-source structure for high gain and large voltage swing. The bias modulator is based on a hybrid buck converter which consists of a linear stage and a switching stage. The dynamic load condition according to the envelope signal level is taken into account for the bias modulator design. By applying the bias modulator to the power amplifier, an overall efficiency of 41.7 % was achieved at an output power of 24 dBm using the 16-QAM uplink LTE signal. It is 5.3 % points higher than that of the power amplifier alone at the same output power and linearity.

Analog-Assisted Digital Capacitorless Low-Dropout Regulator Supporting Wide Load Range

Tang, Nghia,Tang, Yangyang,Zhou, Zhiyuan,Nguyen, Bai,Hong, Wookpyo,Zhang, Philipp,Kim, Jong-Hoon,Heo, Deukhyoun Institute of Electrical and Electronics Engineers 2019 IEEE transactions on industrial electronics Vol.66 No.3

<P>Capacitorless (CL) low-dropout regulators (LDO) have gained significant research interest for point-of-load voltage regulation without off-chip capacitors. While analog CL-LDOs can deliver superior power supply rejection (PSR), digital CL-LDOs are more scalable and efficient. To achieve the advantages of both types, this paper presents a digital CL-LDO with an analog PSR enhancer, delivering strong PSR without compromising scalability and efficiency. Load regulation is performed by an asynchronous digital feedback controller for fast transient response and scalable load drivability. PSR is achieved by a load-insensitive wide-bandwidth analog controller. A prototype chip of the analog-assisted digital CL-LDO is fabricated in a 130-nm CMOS process with an active area of 0.0645 mm<SUP>2</SUP> , supporting load current up to 50 mA at nominal 1-V input and 0.8-V output. The measured PSR is better than –20 dB for frequencies up to 10 MHz, and the measured current efficiency peaks at 99.3%, with average current efficiency of 96.7% across 50× load range. The measured transient response to a full load step, with two values of load capacitance (100 pF and 10 nF), demonstrates the LDO's stable operation over a wide range of load resistance and capacitance.</P>

CMOS Power Amplifier Integrated Circuit With Dual-Mode Supply Modulator for Mobile Terminals

Junghyun Ham,Jongseok Bae,Hyungchul Kim,Mincheol Seo,Hwiseob Lee,Keum Cheol Hwang,Kang-Yoon Lee,Cheon-seok Park,Deukhyoun Heo,Youngoo Yang IEEE 2016 IEEE Transactions on Circuits and Systems I: Regul Vol.63 No.1

<P>A CMOS power amplifier integrated circuit with an optimized dual-mode supply modulator is presented. The dual-mode supplymodulator, based on a hybrid buck converter consisting of a wideband linear amplifier and a highly efficient switching amplifier, provides two operation modes: envelope tracking (ET) for high average output power and average power tracking (APT) for low output power. For the APT mode, the linear amplifier is switched off and the switching amplifier operates as a normal buck converter to supply DC voltage to the power amplifier according to the average output power. The optimum switch sizes of the switching amplifier were analyzed and applied for each operation mode for higher efficiency. An integrated circuit with a power amplifier and the dual-mode supply modulator was designed and fabricated using a 0.18-mu m CMOS process for LTE applications at a frequency of 0.78 GHz. For the 16-QAM uplink LTE signal, the measured efficiency with an ET mode is as high as 45.4%, which is 7.0% higher than that from the stand-alone power amplifier at an average output power of 24 dBm. An efficiency of 14.1% was achieved with an APT mode at an average output power of 9 dBm. This is 3.2% higher than that with the ET mode.</P>

Switched Substrate-Shield-Based Low-Loss CMOS Inductors for Wide Tuning Range VCOs

Agarwal, Pawan,Sah, Suman Prasad,Molavi, Reza,Mirabbasi, Shahriar,Pande, Partha Pratim,Oh, Seung Eel,Kim, Jong-Hoon,Heo, Deukhyoun Professional Technical Group on Microwace Theory a 2017 IEEE Transactions on Microwave Theory and Techniqu Vol. No.

<P>A switched substrate-shield inductor (SSI) topology in bulk CMOS is proposed which minimizes parasitic capacitance and substrate losses, while tuned magnetically induced currents facilitate inductor tunability. The high frequency behavior of the induced current is analyzed, resulting in intuitive insights and design guidelines for a high-performance SSI. An SSI prototype in 65-nm bulk CMOS achieves 34% inductance tunability with a quality factor of >10.3. A voltage-controlled oscillator (VCO) using SSI achieves 40.3% tuning range, from 21 to 31.6 GHz, and a phase noise of -119.1 ± 3.7 dBc/Hz at 10-MHz offset frequencies. The VCO core consumes 4.3 ± 0.2 mW from a 1-V supply.</P>

Inductor-less SiGe pin diode attenuator with low phase variations

Zhu, S.,Mikul, A.O.,Sun, P.,You, Y.,Kim, Jong-Hoon,Kim, Byeong-Sam,Heo, Deukhyoun IET 2012 Electronics letters Vol.48 No.20

<P>An inductor-less wideband (6-18 GHz) 3-bit attenuator with low phase variations is presented based on octagonal SiGe p-type intrinsic n-type ( pin) diodes. To achieve low insertion loss and high linearity, a DC bias scheme has been designed to minimise the leakage from the parasitic diodes between the P-sub and N-well of the pin diodes. The attenuator is fabricated in a standard 0.18 mm SiGe BiCMOS process without using post-processed transmission lines. It has a maximum attenuation range of 7 dB. The minimum measured insertion loss is 7.9, 9.4, 10.6 dB at 6, 12, 18 GHz, respectively. Phase variation is lower than ± 2.5° and the chip size, including pads, is 0.85 x 0.412 mm<SUP>2</SUP>.</P>