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DSP 기능을 내장한 32비트 RISC 마이크로프로세스 설계
최병윤 東義大學校 産業技術開發硏究所 1997 産業技術硏究誌 Vol.11 No.-
This paper describes a 32-bit RISC microprocessor which has been designed for embedded DSP applications. To support compact code of embedded application, this processor adopts new architecture which can execute both 16-bit instructions and 32-bit instruction through 32 bit RISC core and decompressor. Futher, to satisfy fast MAC (multiplication & accumulation) operation of DSP, the processor has dedicated hardware multiplier which can complete 32-bit by 32-bit integer multiplication within four clock cycles. This architecture is based on RISK principles. The processor adopts 3-stage instruction execution pipeline and has achieved single cycle execution using a 2-phase 40MHz clock. This results in a high instruction throughput and 5-cycle interrupt response time. This chip is implemented with 0.6㎛ triple metal CMOS technology and consists of about 110K transistors.
최병윤 東義大學校 産業技術開發硏究所 1999 産業技術硏究誌 Vol.13 No.-
In this paper EPR-4 viterbi decoder for magnetic disk read channel is designed. The viterbi decoder consists of ACS circuit, path memory circuit, minimum detection circuit, and output selection circuit. In the viterbi decoder the number of state is reduced from 8 to 6 using (1,7) RLL codes and modulo comparison based on 2'5 complement arithmetic is applied to handle overflow problem of ACS module. Also to determine the correct symbol values in nonconvergent condition of path memory, pipelined minimum detector which determines path with minimum state metric is used. The EPR-4 viterbi decoder is designed using MOSIS 0.35㎛ CMOS technology and consists of about 15,300 transistors and has 250 Mbps data rates under 3.30 volts.
수퍼스칼라 마이크로프로세서용 부동 소숫점 승산기의 VLSI 설계
최병윤 東義大學校 産業技術開發硏究所 1996 産業技術硏究誌 Vol.10 No.-
This paper describes a 54-bit multiplier of floating-point of floating-point arithmetic unit for superscalar microprocessor designed by 0.6um CMOS technology. This multiplier adopts modified booth algorithm and redundent signed-digit number system to offer high speed operation and regular layout. It can execute 2's complement 54 bit by 54 bit multiplication through 2-stage pipelined datapath and consists of new booth encoder, partial product generator generator(PP-GEN), signed digit partial product(PP-SD-GEN), rudundant binary adder tree, and RB-to-NB converter. To verify and ensure the operation and performance of the designed multiplier, intensive simulations have been performed with Hspice simulator. Verilog HDL Simulator, and Compas Qsim simulator. This simulation results show that the designed multiplier achieves a peak performance of 100Mhz operating frequency with 2-cycle latency and 1-cycle throughput and has high performance required in the superscalar microprocessor.