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Suppression Subtractive Hybridization을 통한 Venturia Nashicola 접종후 ‘93-3-98’에서 유도된 저항성 후보 유전자 선발
천재안(Jae-An Chun),남가영(Ga-Young Nam),김세희(Se-Hee Kim),조강희(Kang-Hee Cho),김대현(Dae-Hyun Kim),최인명(In-Myeong Choi),신일섭(Il-Sheob Shin) 한국육종학회 2015 한국육종학회지 Vol.47 No.1
Suppression subtractive hybridization was carried out to identify resistant genes against to pear scab caused by Venturia nashicola using leaves harvested at 24 and 48 hours after inoculation into ’93-3-98’ (highly resistant) and ‘Sweat Skin’ (highly susceptible). As a result of the ESTs analysis, nine and 14 unique genes were expressed on 24H (tester, mRNA at 24hr after inoculation of ’93-3-98’; driver, one of ‘Sweet Skin’) and 48H (tester, mRNA at 48hr after inoculation of ’93-3-98’; driver, one of ‘Sweet Skin’), respectively and genes related to defense or stress response were accounted for 40% (24H) and 42% (48H). Differential expressed genes classifying into PR protein family were pathogenesis-related protein 1a, major allergen Pyr c1 and allergen mal d 1 at 24H and major allergen Mal d 1.03B at 48H, respectively. Major allergen Pyr c1, F-Box/kelch-repeat protein, Flavoprotein wrbA, and hypothetical protein POPTRDRAFT_783792 are expected to closely connecting to scab resistance of pear following strongly expressed in highly resistant cv. ‘Bartlett’ and ‘93-3-98’ compared with moderately susceptible cv. ‘Gamcheonbae’, susceptible cv. ‘Wonhwang’, and highly susceptible cv. ‘Niitaka’ and ‘Sweat skin’.
소모 전력이 적은 12비트 1MSps 축차 비교형 아날로그-디지털 변환기 설계
천재일(Jae-Il Chun),최예지(Ye-Ji Choi),류지열(Jee-Youl Ryu) 제어로봇시스템학회 2021 제어·로봇·시스템학회 논문지 Vol.27 No.1
In this paper, a low-power 12-bit 1MSps Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) is proposed to increase the integration degree. The proposed circuit is designed using the 1Poly-6Metal 0.13 ㎛ CMOS process, and operates at a supply voltage of 1.2 V. A pre-amplifier is incorporated to amplify both comparator and buffer, and offer flexible signal processing and good performance. The signal processing stage is compared to conventional circuits, so that fine signals can be captured for optimization. The proposed ADC showed very low power consumption (0.654 ㎽), good Figure of Merit (FOM) (0.98 fJ/conversion) and smaller die area (0.106 ㎟) compared with conventional results. This circuit also showed excellent Effective Number of Bits (ENOB) and high Signal-to-Noise Distortion Ratio (SNDR), 72.19 ㏈ and 11.69 bits respectively.
Design of Programmable Finite Impulse Response Filter
Jae-Il Chun(천재일),Ye-Ji Choi(최예지),Keun-Pil Kil(길근필),Myeong-U Sung(성명우),Shin-Gon Kim(김신곤),Murod Kurbanov(무로드 쿠르바노프),Delwar Tahesin Samira(델워 타헤신 사미라),Abrar Siddique(시디크 아브라르),Prangyadarsini Behera(파랑야다시 한국정보통신학회 2019 한국정보통신학회 종합학술대회 논문집 Vol.23 No.2
직류 오프셋 제거 회로를 가진 저 전력 프로그램 가능한 이득 증폭기 설계
최예지(Ye-Ji Choi),천재일(Jae-Il Chun),류지열(Jee-Youl Ryu) 제어로봇시스템학회 2020 제어·로봇·시스템학회 논문지 Vol.26 No.10
In this paper, a low-power gain control amplifier with a direct current offset cancellation circuit is proposed in order to amplify analog signals. The proposed PGA (Programmable Gain Amplifier) is less sensitive to external influences due to the inclusion of active load on differential amplifiers. The PGA connects a direct current offset cancellation circuit, based on the Miller effect, to a differential amplifier stage to reduce area and compensate for distortion or lack of linearity. This circuit is also designed to be adjustable in eight steps, from 4 dB to 60 dB, using gain controls. The proposed PGA is designed using the TSMC 0.13 μm CMOS process, and was verified by simulation in ADS (Advanced Design System) tool. Compared to conventional research results, the proposed PGA achieved a gain error of less than 0.1 dB and a lower consumption of 0.16 mW.