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신호 대 잡음비가 향상된 센서 신호 측정용 저 전력 SAR형 A/D 변환기
정찬경 ( Chan-kyeong Jung ),임신일 ( Shin-il Lim ) 한국센서학회 2018 센서학회지 Vol.27 No.1
This paper describes a low-power, SNDR (signal-to-noise and distortion ration) enhanced SAR (successive approximation register) type 12b ADC (analog-to-digital converter) with noise shaping technique. For low power consumption and small chip size of the DAC (digital-to- analog converter), the top plate sampling technique and the dummy capacitor switching technique are used to implement 12b operation with a 10b capacitor array in DAC. Noise shaping technique is applied to improve the SNDR by reducing the errors from the mismatching of DAC capacitor arrays, the errors caused by attenuation capacitor and the errors from the comparator noise. The proposed SAR ADC is designed with a 0.18 μm CMOS process. The simulation results show that the SNDR of the SAR ADC without the noise shaping technique is 71 dB and that of the SAR ADC with the noise shaping technique is 84 dB. We can achieve the 13 dB improvement in SNDR with this noise shaping technique. The power consumption is 73.8 μW and the FoM (figure-of-merit) is 5.2fJ/ conversion-step.