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열차폐 코팅을 위한 지르코니아계 세라믹 소재의 기계적 특성
정규익,김태우,백문규,이기성,Jung, Kyu-Ick,Kim, Tae-Woo,Paik, Ungyu,Lee, Kee-Sung 한국세라믹학회 2006 한국세라믹학회지 Vol.43 No.8
A gas turbine blade with thermal barrier ceramic coating is operated at high temperature to increase engine efficiency. Recently, thermal barrier characteristics have been improved by advanced coating technology through microstructure control and increase of adhesion force of the coating layer. More advanced coating materials, rare earth zircon ate ceramics have been studied for replacing YSZ coatings as thermal barrier coatings. In this study, $La_2O_3,\;HfO_2,\;CeO_2,\;Gd_2O_3$ and pure or yttria stabilized zirconia were prepared. Microstructure analysis and the evaluation of mechanical properties such as Hertzian indentation and hardness test were performed.
정규익(Kyu Ick Jung),김태우(Tae Woo Kim),백운규(Unkyu Paik),이기성(Kee Sung Lee) 대한기계학회 2006 대한기계학회 춘추학술대회 Vol.2006 No.11
A gas turbine blade is operated at high temperature to increase engine efficiency and improve blade performance. For this purpose, TBCs(Thermal barrier coatings) are used on advanced turbine blade. Due to severe operation conditions, the evaluation of creep, fatigue, corrosion and indentation stress are important. In this study, we prepared multi-layered system for TBCs, which protects inside metallic component from external damage such as collision of fine particle. The difference of CTE between the coating layer and the substrate causes residual stress in the coating layer. Therefore, we designed that the outer layer of the multi-layered system has a good resistance from contact damage and inner layer has similar CTE to lower bond-coat layer. Especially we investigated the indentation behavior using Hertzian and Vickers indentation technique.
임호정,정규익,김지현,Ruben Fuentes 한국마이크로전자및패키징학회 2017 마이크로전자 및 패키징학회지 Vol.24 No.4
Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.
이승모(Cheng Mo Li),정규익(Kyu Ick Jung),김철(Chul Kim),김태우(Tae Woo Kim),임홍재(Hong Jae Yim),이기성(Kee Sung Lee) 대한기계학회 2006 대한기계학회 춘추학술대회 Vol.2006 No.11
Recently the process and the property of nano material are widely investigated due to its excellent properties. The controlling of nano-sized grain by heat treatment is investigated. Different sizes of nano- and micro- grains are controlled using different heating schedule during pressurized sintering process or varying the substrate temperatures during electron beam physical vapor deposition. Electron microscopy examination and X-ray diffraction confirms that the nano-size of semiconductor sample, which is respectively heat-treated at 1750℃ and 1550℃ in Ar, is controlled from 30㎚ to 50㎚, and after heat-treatment of 600℃, 700℃, 800℃, 900℃ the grain size of ion-conductor sample is varying with substrate temperature.