잉여수계 신경망의 고속 연산 알고리즘에 관한 연구

尹賢植 忠州大學校 1998 한국교통대학교 논문집 Vol.33 No.2

We propose a design algorithm for fast computation and shrinking the hardware size of the sigmoid function generator in digital neural networks(DNN). Because the DNN is composed of massive distributed parallelism and a lot of data buses, it needs a high speed processors and small hardware structure in the same time. The proposed algorithm is superior to the digital neural network system with floating point processing structure in the same conditions. From the results of computer simulation, Look-up table should be taken larger size in order to converging target error under 10??, because accuracy of neural network applications decide modulo and in that case, sigmoid function values in the look-up table are changed with I/O values and error degrees. The proposed algorithm is avaliable to the pattern recognition field for the merit of residue number system.

最小테스트數를 要하는 論理回路의 實現에 關한 硏究

尹賢植 忠州大學校 1982 한국교통대학교 논문집 Vol.15 No.1

This paper is an investigation of the design of combinational logic circuits which require a minimal number of fault detection tests. Based on the path sensitizing concepts, the patterns for the primary input gates of the network are defined, and then it is shown that, arranging these predefined test patterns according to the path sensitizing characteristics of the given network structures, the minimal complete test sets for fan-out free combinational networks can be found easily. It is also shown that, taking into account the fanout paths sensitizing compatibility, the proposed method can be extended to the irredundant reconvergent fan-out networks.

마이크로 프로세서用 가상기억체제에 關한 硏究

尹賢植 忠州大學校 1985 한국교통대학교 논문집 Vol.19 No.1

This thesis introduces a virtual memory system which may be connected to the memory bus of a host computer. The sistem is based on the use of a separate processor to interface to the auxiliary memory and perform all the processing related to manging the virtual memory. The proposed approach provides a virtual memory that is transparent to the host processer, with one exception. When a memory reference generated by the host result in a pag efault, a long delay is encountered. This delay corresponds to the time taken by the virtual memory controller to carry outa page transfer. Bubble memory devices are used to implement the auxiliary memory. The suitability of bubble memories in this environment is discussed in the thesis.

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윤현식 (주)매일경제신문사 2020 매경럭스맨 Vol.- No.122

Optimizing the Optical Properties of Fluorine-doped ZnO Thin Films Deposited by Sol-gel Spin-coating

윤현식,최현광,임재영,이상헌,김진수,김종수,손정식 한국물리학회 2014 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.65 No.4

The optical properties of sol-gel spin-coated ZnO and F-doped ZnO (FZO) thin films were investigatedusing ultraviolet-visible and temperature-dependent photoluminescence spectroscopies. TheFZO films showed on average of > 80% optical transmittance over the entire visible region, and thetransmittance spectra and the optical bandgaps were blueshifted owing to the Burstein-Moss effect. The 4 at% FZO film showed the lowest Urbach energy and, thus, the best crystallinity of all the films. Changes in the free exciton, neutral-donor-bound exciton (D0X), donor-acceptor pair, and secondorderlongitudinal optical phonon replica peaks were represented from the temperature-dependentphotoluminescence spectra. The strength of the exciton-phonon coupling was investigated usingthe Bose-Einstein approximation to fit the experimental data, and the thermal activation energiesof the as-deposited ZnO and 4 at% FZO thin films were determined using Arrhenius plots for theintegrated PL intensities of the D0X peak.

시스톨릭 어레이 프로세서에 의한 인공신경회로망의 구현

尹賢植 忠州大學校 1991 한국교통대학교 논문집 Vol.25 No.-

In this paper, back-propagation neural network using systolic array processor is presented. The proposed design is based on the classical systolic algorithm of matrix-by-vecter multiplication. Systolic array circuit architecture with Residue Number System is suggested to realize the efficient arithmetic circuit for matrix-by-vector multiplication and computing sigmoid function. This method of design shows that the speed of parallel processing is high and the hardware structure is simple.

Effect of thermal boundary condition of an inner cube on three-dimensional natural convection in a cubical

윤현식,J. H. Jung,H. S. Lee,B. Y. Koo 대한기계학회 2015 JOURNAL OF MECHANICAL SCIENCE AND TECHNOLOGY Vol.29 No.10

We numerically investigated three-dimensional (3-D) natural convection in a vertical cubic enclosure with an inner cube for Rayleighnumbers (Ra) in the range of 103 £ Ra £106 . For the inner cube at the center, four different thermal boundary conditions (adiabatic,neutral, and hot and cold isothermal conditions) were considered in order to investigate their effect on flow and thermal fields. ForRa =103 and Ra =104 , single circulation appears regardless of the thermal boundary condition of the inner cube. When Ra =105and Ra =106 , the combined effects of the inner cube as a bluff body and the thermal condition imposed on the inner cube on the fluidflow and thermal fields are significant, and intensify the 3-D effect. Generally, for Ra =105 and Ra =106 , the convective flow ischaracterized by the formation of two inner vortices embedded in the primary circulation, and by secondary vortices due to flow separationat the edge of the inner body. As Ra increases, the local Nusselt number varies rapidly in the vertical direction, which is supported bythe temperature isosurfaces that form an S-shape. The total surface-averaged Nusselt numbers for the different cases have approximatelythe same profile with respect to the Rayleigh number as the power function.

페이지 기억체계를 지닌 데이타흐름구조의 설계

윤현식 忠州大學校 1986 한국교통대학교 논문집 Vol.20 No.1

The paper presents a data flow architecture with a paged memory system to hold both data flow programs and data structures. The token labeling mechenism is coupled with the memory management system in order to provide for each token a unique memory location. The instruction format allows instructions with multiple operands and multiple destinations for each result Data structures are held in memory while pointers to the structures are circulating as tokens.

대형 와 모사를 통한 레이놀즈 수 증가에 따른 혼합 탱크 내의 유동 구조의 연구

윤현식,전호환,하만영,Yoon, Hyun-Sik,Chun, Ho-Hwan,Ha, Man-Yeong 대한기계학회 2003 大韓機械學會論文集B Vol.27 No.9

The stirred tank reactor is one of the most commonly used devices in industry for achieving mixing and reaction. Here we report on results obtained from the large eddy simulations of flow inside the tank performed using a spectral multi-domain technique. The computations were driven by specifying the impeller-induced flow at the blade tip radius. Stereoscopic PlY measurements (Hill et al. $^{(1)}$) along with the theoretical model of the impeller-induced flow (Yoon et al. $^{(2)}$) were used in defining the impeller-induced flow as superposition of circumferential, jet and tip vortex pair components. Large eddy simulation of flow in a stirred tank was carried out for the three different Reynolds numbers of 4000, 16000 and 64000. The effect of different Reynolds numbers is well observed in both instantaneous and time averaged flow fields. The instantaneous and mean vortex structures are identified by plotting an isosurfaces of swirling strength for all Reynolds numbers. The Reynolds number dependency of the non-dimensional eddy viscosity, resolved scale and subgrid scale dissipations is clearly shown in this study.

디지탈 神經回路網 設計에 관한 硏究

尹賢植 충주대학교 1992 한국교통대학교 논문집 Vol.26 No.-

In this paper, we will present an array processor for the implementation of digital neural networks. Back-propagation model can be formulated as a consecutive matrix-vector multiplication problem with some prespecified thresholding operation. This structure suited for the design of array processor, because the operation procedure can be recursively and repeatedly executed. Systolic array circuit architecture with Residue Number System is suggested to realize the efficient arithmetic circuit for matrix-vector multiplication and computing sigmoid function. The proposed design method expected to adopt for application field of neural networks because it can be realized to currently developed VLSI technology.