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Post-Metallization Annealing 시 passivation 막이 나노 NMOSFET 용 I/O 소자의 핫-캐리어 특성에 미치는 영향
유욱상(Ooksang Yoo),한인식(Inshik Han),주한수(Hansoo Joo),손영환(Younghwan Son),구태규(Taegyu goo),최원호(Wonho Choi),최성욱(Seongwook Choi),임민규(Mingyu Lim),강영석(Youngseok Kang),이정환(Junghwan Lee),왕진석(Jinsuk Wang),이가원(Gawon 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
In this paper, we analyze effect of passivation(Si₃N₄ film) condition under Post-Metallization Annealing on hot carrier degradation. Very thick Si₃N₄(≥ 10000A) prevents H₂ from diffusing into interface(Si-SiO₂), so that hot carrier degradation gets severe. Therefore PMA is performed before Si₃N₄ deposition for hot carrier immunity.
Hot carrier 개선을 위한 N2 이온주입에 따른 MOSFET의 Digital/Analog 특성 분석
구태규(Taegyu Goo),한인식(Inshik Han),유욱상(Ooksang Yoo),주한수(Hansoo Joo),최원호(Wonho Choi),손영환(Younghwan Son),이정환(Jeonghwan Lee),강영석(Younseok Kang),임민규(Mingyu Lim),최성욱(Seongwook Chio),이가원(Gawon Lee),왕진석(Jinseok 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
In this paper, we investigated the performance and reliability of the device as formatting LDD(Lightly Doped Drain) with additional N₂ implant process. In case of the N₂ implantation, the TED(Transient Enhanced Diffusion) of boron is suppressed in channel regime and the drain current increased. But hot carrier lifetime is improved. Also, we investigated a change of the effective channel length using CP(Charge Pumping) current method and the analog performance is compared to evaluate DC gain and Rout according N₂ implantation. However, the N₂ implantation did not affect at analog performance. But the drain current at the normalized threshold voltage is degraded in digital performance. Therefore, we proved that the reliability can be improved without degrading Rout performance. The important Input/Output(IO) device in the analog performance is partially adapted for nano CMOS technology.