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Bongsu Kim(김봉수),Songi Cheon(천송이),Seung-Myeong Yu(유승명),Jongchan An(안종찬),Gwangmyeong An(안광명),Yoonsang Lee(이윤상),Hyunsu Jang(장현수),Junyoung Song(송준영) 대한전자공학회 2024 대한전자공학회 학술대회 Vol.2024 No.6
This paper presents an output capacitor-less low-dropout regulator (LDO) that achieves high power supply rejection (PSR) and low peak-to-peak deviation using multiple paths when the burst mode output load changes rapidly. By adjusting the output voltage with a compensation signal proportional to the power supply noise, feedforward cancellation enhances the PSR in the LDO. The pole position in the global feedback loop (GFL) was adjusted using two buffers to ensure high PSR at high frequency. The proposed LDO achieves a worst case -59.1 dB PSR up to 100 MHz for a load current of 10 mA. Furthermore, the peak-to-peak deviation of 13.4 mVp-p was shown when the load current changed from 200 uA to 10 mA, and the figure of merit was 0.852 ps. This work was fabricated in CMOS 28 nm technology and occupies an active area of 0.014 mm².