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Punchthrough 원통형 접합이 항복전압에 대한 해석적 모델
배동건,정상구 대한전자공학회 1999 電子工學會論文誌, D Vol.d36 No.4
Analytic model for punchthrough limited breakdown voltage of cylindrical junction is presented as a function of the epitaxial layer thickness and the critical depletion width of the cylindrical junction in nonpunchthrough cases. All the expressions for the distances, electric fields and potentials are normalized, allowing quick determination of the corresponding breakdown voltages. The calculated results are in good agreement with the simulations obtained from two dimensional device simulation program MEDICI. Punchthroush 원통형 접합의 항복전압에 대한 해석적 모델을 에피층의 두께와 nonpunchthrough 원통형 접합의 항복시 임계공핍영역폭이 함수로 제안하였다. 이 해석적 모델에서의 모든 거리변수와 전계 및 전위식을 정규화된 형태로 사용하므로써 항복전압을 소자의 물리적 parameter에 관계없이 쉽게 결정할 수 있게 하였다. 제안된 모델의 계산결과를 2차원 소자 Simulation Program인 MEDICI를 사용하여 얻은 결과와 비교하여 매우 잘 일치함을 보였다.
배동건,정상구,Bae, Dong-Gun,Chung, Sang-Koo The Institute of Electronics and Information Engin 1986 전자공학회논문지 Vol.23 No.6
Measurements of interface states in a MOS capacitor by DLTS system using wideband monophase lock-in amplifier are discussed. A new signal analysis method that takes into account the bias pulse width and the gate off width is presented to remove the errors in the measured parameters of interface states resulting from the traditional method which neglects the effect of those widths. Theoretical calculations are made for the parameters related to the rate window, signal to noise ratio, and the energy resolution. On the grounds of this discussion, interface states of the MOS capacitor on p-type substrate of (110) orentation are measured with the optimal gate-off width with respect to the S/N ratio and the energy resolution. The results are interface state density of the order of 10**10 (cm-\ulcornereV**-1) to 10**11 (cm-\ulcornereV**-1) in the energy range of Ev+0.15(dV) to Ev+0.5(eV), and constant capture cross section of the order of 10**-16 (cm\ulcorner.
SOI LDMOS에서 선형 Field Plate 의 항복전압 특성에 관한 연구
배동건 거제전문대학 1997 論文集 Vol.5 No.-
An SOI LDMOS(Silicon-On-Insulator Laterally Double diffused MOS) with tapered field plate which has more superior breakdown characteristics in comparison with conventional SOI LDMOS with stepped field plate is proposed. Comparing two structures using 2-D simulator, MEDICI, the proposed structure shows that the surface electric field can be decreased more effectively and has wider range of drift region thickness and of field plate length. The two structures are fabricated and compared in terms of breakdown characteristics. The enhanced breakdown voltage of LDMOS with tapered field plate is verified by 143V of breakdown voltage in excess of 74%.
다수의 전계제한링을 갖는 planar소자의 해석적 모델
배동건,정상구 대한전자공학회 1996 전자공학회논문지-A Vol.33 No.6
A simple analytic model for the planar junctions with multiple foating field limiting rings(FLR) is presented which yields analytic expressions for the breakdown voltage and optimum ring spacings. the normalized potential of each ring is derived as a function of the normalized depletion width and the ring spacing. Based on the assumption that the breakdwon occurs simulataneously at cylindrical junctions of FLR structure where the peak sruface electric fields are equal, the optimum ring spacings are determined. The resutls are in good agreement with the simulations obtained from two dimensional device simulation program MEDICI and with the experimental data reported. The normalized experessions allow a calculation of breakdown voltage and optimum spacing over a broad range of junction depth and background doping levels.