GF ( 2m ) 상의 산술연산기시스템 구성 논리 ( A Construction Theory of Arithmetic Operation Unit Systems over GF ( 2m ) )

박춘명,김흥수 대한전자공학회 1990 전자공학회논문지 Vol.27 No.6

다치논리에 기초한 임베디드시스템구성에 관한 연구

박춘명 忠州大學校 2005 한국교통대학교 논문집 Vol.40 No.2

This paper presents three novel cache models using Multiple-valued Logic(MVL) paradigm to educe the cache data storage area and cache energy consumption for embedded systems. Multiple-valued logic caches have significant potential for compact and power-efficient cache array esign. The cache models differ from each other depending on whether they store tag and data in binary, radix-r or mix or both. Our analytical study of cache silicon area shows that an embedded System-on-a-Chip(SoC)equipped with multiple-valued logic cache model can reduce the cache data storage area up to 6% egardless of cache parameters. Also, our experiments on several embedded benchmarks demonstrate that dynamic cache energy consumption can be reduced up to 62% in a multiple-valued logic instruction cache in an mbedded SoC.

GFDD에 基礎환 多値論理 디지탈시스템設計

朴春明 忠州大學校 1998 한국교통대학교 논문집 Vol.33 No.2

This paper proposes the design method about constructing the Multiple-Valued Logic Digital Systems(MVLDS) over Galois Fields used by the Galois Field Decision Diagram(GFDD) that is based on the Graph Theory. The proposed design method is as follows. First of all, we discuss the mathematical properties of the Galois Fields and the basic properties of the Graph Theory. After we discuss the operational domain and the functional domain, we obtain the transformation matrixes, Ψ?? and ζ??, in the case of one variable, that easily manipulate the relationship between two domains. And we extend above transformation matrixes to n-variable case, we obtain Ψ?? and ζ??. We discuss the Reed-Muller Expansion in order to obtain the multiple-valued logic switching functions of the P-valued single variable. And for the purpose of extending above Reed-Muller Expansion to more two variables, we describe the Kronecker product arithmetic operation. We discuss the method to extract final GFDD after proposing the concepts of the Operational Domain Truth Vector(ODTV) and Functional Domain Truth Vactor(FDTV). Finally, we propose the basic module BM in order to design the circuit of the multiple-valued logic switching function. Next we propose the method of the circuit design for the P-valued n-variables multiple-valued logic switching functions over Galois Field GF(P) based on the BM. The proposed design method is more regular, extensibe and more smaller than the exixting earlier method.

그래프에 기초한 스위칭함수 구현

박춘명,Park, Chun-Myoung 한국정보통신학회 2011 한국정보통신학회논문지 Vol.15 No.9

본 논문에서는 그래프에 기초하여 유한체상의 스위칭함수를 도출하는 알고리즘과 이를 바탕으로 스위칭함수를 회로로 구현하는 방법을 제안하였다. 방향성그래프의 경로 수로부터 행렬방정식을 유도한 후에 이에 따른 스위칭 함수회로설계 알고리즘을 제안하였으며, 설계된 회로와 함께 방향성 그래프의 특성을 만족할 수 있게 노드들에 대한 코드를 할당하는 알고리즘을 제안하였다. 본 논문에서 제안한 알고리즘을 통해 설계한 스위칭함수회로는 기존의 방법에 비해 좀 더 최적화된 스위칭함수회로를 구현할 수 있었으며, 제안한 스위칭함수회로설계 알고리즘을 통해 임의의 자연수의 경로 수를 갖는 방향성 그래프에 대한 설계가 가능하였다. 또한, 입출력단자 수의 감소, 회로구성의 간략화, 연산속도의 향상과 비용감소 등의 이점이 있었다. This paper proposes the method of switching function implementation using switching function extraction based on graph over finite fields. After we deduce the matrix equation from path number of directional graph, we propose the switching function circuit algorithm, also we propose the code assignment algorithm for nodes which is satisfied the directional graph characteristics with designed circuits. We can implement more optimal switching function compare with former algorithm, also we can design the switching function circuit which have any natural number path through the proposed switching function circuit implementation algorithms. Also the proposed switching function implementation using graph theory over finite fields have decrement number of input-output, circuit construction simplification, increment arithmetic speed and decrement cost etc.

기저변환에 기반을 둔 진보된 곱셈기 구성에 관한 연구

박춘명 한국교통대학교 2015 한국교통대학교 논문집 Vol.50 No.-

This paper proposes the effective multiplier using basis transformation. Th proposed multiplier is composed of the standard-dual basis transformation circuit module to change one input into dual basis the operation module to generate from bm to bm+k by the m degree irreducible polynomial, and the polynomial multiplicative module to consist of m2 AND and m(m-1) EX-OR gates. Also, the dual-standard basis transformation circuit module to change the output part to be shown as a dual basis into standard basis is composed. The operation modules to need in each operational part are defined.

De Bruijn 그래프에 의한 다중처리기 구성

박춘명,Park, Chun-Myoung 한국정보통신학회 2006 한국정보통신학회논문지 Vol.10 No.12

본 논문에서는 De Bruijn그래프에 기초한 다중처리기 구성 방법에 대해 논의하였다. 유한체 상의 수학적 성질과 그래프의 성질을 사용하여 변환연산자에 대해 논의하였으며, 이들 변환연산자를 이용하여 De Buijn그래프의 변환표를 도출하였다. 그리고, 이 변환표로부터 유한체 상의 De Bruijn 그래프를 도출하였다. 제안한 다중처리기는 유한체 상에서의 임의 소수와 양의 정수에 대해 구성할 수 있으며 고장허용컴퓨팅 시스템, 파이프라인 시스템, 병렬처리 네트워크, 스위칭 함수와 이의 회로, 차세대 디지털논리 시스템 및 컴퓨터 구조 등에 적 용할 수 있다. This paper presents a method of constructing the universal multiple processing element unit(UMPEU) by De Bruijn Graph. The second method is as following. First, we propose transformation operators in order to construct the De Bruijn UMPEU using properties of graph. Second, we construct the transformation table of De Bruijn graph using above transformation operators. Finally we construct the De Bruijn graph using transformation table. The proposed UMPEU be able to construct the De Bruijn graph for any prime number and integer value of finite fields. Also the UMPEU is applied to fault-tolerant computing system, pipeline class. parallel processing network, switching function and its circuits.

임베이드시스템에 基礎한 시스템온칩에 관한 硏究

박춘명 忠州大學校 2003 한국교통대학교 논문집 Vol.38 No.3

This paper presents a method of constructing the system-on-chip based on embedded systems. The proposed method is more compact and effectiveness than former methods. The requirements generation start high level performance simulation and then passes to an executable specification suitable for implementation using a hardware/software co-design tool. The reuse of pre-existing components is supported, as well as synthesis of the system interface, but only after much work is done to program the hardware/software co-design tool. The actual design flow described allows feedback among all design levels, e.g. from implementation up to requirements, throughout the process. In the future, it is necessary to development the advanced method of constructing system-on-chip based on embedded systems.

하드웨어/소프트웨어 통합설계에 기초한 임베이드시스템 구성

朴春明 충주대 2003 産業科學論文集 Vol.11 No.-

This paper presents a hardware/software co-design approach where different specification languages can be used in parallel, allowing effective system co-modeling. The proposed methodology introduces a process model that extends the traditional spiral model so as to reflect the design needs of modern embedded systems.

유비쿼터스컴퓨팅 환경에 기반을 둔 이러닝 모델

박춘명 忠州大學校 2008 한국교통대학교 논문집 Vol.43 No.-

This paper presents a model of e-learning based on ubiquitous computing configuration. First of all, we survey the advanced e-learning systems for foreign and domestic universities. Next we propose the optimal e-learning model based on ubiquitous computing configuration. The proposed e-learning model as following. we propose the e-learning system's hardware and software configurations, that are server and networking systems. Also, we construct the proposed e-learning systems's services. There are attendance and absence service, class management service, common knowledge service, score processing service, facilities management service, personal management service, personal authorization issue management service, campus guide service, lecture-hall management service. Then we propose the laboratory equipment management service, experimental materials management service etc. The proposed model of e-learning based on ubiquitous computing configuration will be able to contribute to the next generation university educational paradigm.

유한체상의 P=3인 경우의 역원 생성기

박춘명 忠州大學校 2011 한국교통대학교 논문집 Vol.46 No.-

This paper presents a method of inverse element generator in case of P=3 over finite field. The proposed method computing inverse of an element over P=3 over finite field which is corresponds to a polynomial over finite field with order less than equal to m-1. Here, the computation is based on multiplication, square and cube method which are derived from the mathematics properties over finite fields.