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류선우(Ryu, Sun-Woo),서태양(Seo, Tai-Yang) 청운대학교 관광산업연구소 2011 관광산업연구 Vol.5 No.1
This study aims to understand the perception of the medical people working in gwangju and jeonnam areas on medical tours through an empirical analysis and to present a plan for its vitalization and expected effects. First, if the medical people working in Gwangju and Jeonnam areas are continuously interested in medical tours and carry out medical tour programs for inspiration, such will be able to bring other medical people ’s active participation and inspire them. Second, an interactive link system among the medical institutions in Gwangju and Jeonnam areas is required through making each hospital a brand based on its specialty. Such link will be able to form a medical tourism belt between medical institutions and tourism complexes. Specialization by medical department may result in small- and medium-sized hospitals ’ participation. Third, medical tours need to be comprehensively promoted at a local government level. Moreover, a specific program to train medical tour experts will be able to train the experts required in theses areas. And finally, the most important things are the local medical people ’s mind and their voluntary participation in medical tours. Beyond a simple interest in a medical tour, the medical people need to put it into action with a positive mind for their hospitals and local society.
장현만,류수림,선우명훈,Chang, Hyun-Man,Ryu, Su-Rim,Sunwoo, Myung-Hoon 대한전자공학회 1999 電子工學會論文誌, C Vol.c36 No.6
본 논문에서는 무선 LAN 표준안 IEEE 802.11의 직접대역확산(Direct Sequence Spread Spectrum) 물리계층을 지원하는 기저대역 모뎀 ASIC 칩의 아키텍쳐와 설계에 대해 기술한다. 구현된 모뎀 칩은 크게 송신부와 수신부로 구성되어 있으며, CRC 부호화/복호화기, 차동 부호화/복호화기, 주파수 옵셋 보상기(frequency offset compensator) 및 타이밍 복구 회로를 포함한다. 구현된 모뎀 칩은 4, 2 및 1Mbps의 다양한 데이타 전송률을 지원하고, DBPSK와 DQPSK의 변조방식을 사용한다. 구현한 모뎀 아키텍쳐는 $SAMSUNG^{TM}$ $0.6{\mu}m$ 게이트 어레이 라이브러리(gate array library)를 사용하여 논리합성을 수행하였으며, 칩의 전체 게이트 수는 53,355개이다. 칩의 동작 주파수는 44MHz이며, 칩의 패키지는 100-pin QFP이고, 전력소모는 44MHz에서 1.2watt이다. 구현된 모뎀 아키텍쳐는 상용화된 HSP3824 칩 보다 우수한 BER성능을 나타낸다. This paper presents the architecture and design of a DSSS MODEM ASIC chip for wireless local area networks (WLAN). The implemented MODEM chip supports the DSSS physical layer specifications of the IEEE 802.11. The chip consits of a transmitter and a receiver which contain a CRC encoder/decoder, a differential encoder/decoder, a frequency offset compensator and a timing recovery circuit. The chip supports various data rates, i.e., 4,2 and 1Mbps and provides both DBPSK and DQPSK for data modulation. We have performed logic synthesis using the $SAMSUNG^{TM}$ $0.6{\mu}m$ gate array library and the implemented chip consists of 53,355 gates. The MODEM chip operates at 44MHz, the package type is 100-pin QFP and the power consumption is 1.2watt at 44MHz. The implemented MODEM architecture shows lower BER compared with the Harris HSP3824.