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CMOS Latch-Up 현상의 실험적 해석 및 그 방지책
고요환,김충기,경종민,Go, Yo-Hwan,Kim, Chung-Gi,Gyeong, Jong-Min 대한전자공학회 1985 전자공학회지 Vol.22 No.5
A common failure mechanism in bulk CMOS integrated circuits is the latch-up of parasitic SCR structure inherent in the bulk CMOS structure. Latch-up triggering and holding charac-teristics have been measured in the test devicrs which include conventional and Schottky-damped CMOS structures with various well depths and n+/p+ spacings. It is demonstrated that Schottky-clamped CMOS is more latch-up immune than conventional bulk CMOS. Finally, the simulation results by circuit simulation program (SPICE) are compared with measured results in order to verify the validity of the latch-up modal composed of nan, pnp transistors and two external resistors.
얕은 소오스/드레인 접합깊이가 deep submicron CMOSFET 소자 특성에 미치는 영향
노광명,고요환,박찬광,황성민,정하풍,정명준 대한전자공학회 1996 전자공학회논문지-A Vol.33 No.4
With the MOsES (mask oxide sidewall etch scheme)process which uses the conventional i-line stepper and isotropic wet etching, CMOSFET's with fine gate pattern of 0.1.mu.m CMOSFET device, the screening oxide is deposited before the low energy ion implantation for source/drain extensions and two step sidewall scheme is adopted. Through the characterization of 0.1.mu.m CMOSFET device, it is found that the screening oxide deposition sheme has larger capability of suppressing the short channel effects than two step sidewall schem. In cse of 200.angs.-thick screening oxide deposition, both NMOSFET and PMOSFET maintain good subthreshold characteristics down to 0.1.mu.m effective channel lengths, and show affordable drain saturation current reduction and low impact ionization rates.
황성민,노광명,정명준,허민,정하풍,서정원,박찬광,고요환,이대훈,Hwang, Seong-Min,Rho, Kwang-Myoung,Chung, Myung-Jun,Huh, Min,Jeong, Ha-Poong,Suh, Jeong-Won,Park, Chan-Kwang,Koh, Yo-Hwan,Lee, Dai-Hoon 대한전자공학회 1995 전자공학회논문지-A Vol.32 No.6
We proposed SAW (Self-Algined Selectively Grown W-Gate) MOSFET structure, and strudied electrical characteristics of the fabricated SAW MOSFETs. The threshold volgate of 0.21${\mu}$m SAW NMOSFET was 0.18 V and that of 0.24 ${\mu}$m SAW PMOSFET was -0.16 V. The subthreshold slope was 74 mV/decade for NMOSFET and 82 mV/decade for PMOSFET. The maximum transconductance of NMOSFET and PMOSFET, at V$_{GS}$=2.5 V and V$_{DS}$=1.5 V, were260 mS/mm and 122 mS/mm. The measured saturation drain current at V$_{GS}$=V$_{DS}$ =2.5 V was 0.574 mA/${\mu}$m for NMOSFET and -0.228 mA/${\mu}$m for PMOSFET. The gate resistance of SAW MOSFET was about m$\Omega$cm and the n+-p junction capacitance of SAW MOSFET was about 10% lowas than that of the conventional MOSFET's.