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Vector-radix 2차원 고속 DCT의 VLSI 어레이 구현
강용섬,전흥우,신경욱 대한전자공학회 1995 전자공학회논문지-A Vol.32 No.1
An arry circuit is designed for parallel computation of vector-radix 2-D discrete cosine transform (VR-FCT) which is a fast algorithm of DCT. By using a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently implemented with high condurrency and local communication geometry. The proposed implementation features architectural medularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. The array core for (8$\times$8) 2-D DCT, which is designed usign ISRC 1.5.mu.m N-Well CMOS technology, consists of 64 PEs arranged in (8$\times$8) 2-D array and contains about 98,000 transistors on an area of 138mm$^{2}$. From simulation results, it is estimated that (8$\times$8) 2-D DCT can be computed in about 0.88 .mu.sec at 50 MHz clock frequency, resulting in the throughput rate of about 72${\times}10^[6}$ pixels per second.
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2차원 어레이를 이용한 Vector-radix 2차원 고속 DCT의 효율적인 VLSI 구현
신경욱,전흥우,강용섬 金烏工科大學校 1993 論文集 Vol.14 No.-
This paper describes an efficient array algorithm for parallel computation of vector-radix two-dimensional (2-D) fast discrete cosine transform(VR-FCT), and its VLSI implementation. The proposed array algorithm features architectural modularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. It has the time complexity of ?? for (N X N) 2-D DCT, where ?? is the number of non-zero digits in canonic-signed digit (CSD) code. An array core based on the proposed array algorithm is designed with ISRC 1.5㎛ double metal N-Well CMOS technology. A hierarchical design approach based on Bit-Slice Unit (BSU) is adopted to achieve simple design and regular interconnections. The designed array core consists of 64 PE's arranged in 8 rows 8 columns, and it contains about 98,000 transistors on an area of 138㎜²excluding control logic block. From simulation results, it is estimated that (8X8) 2-D DCT(??) can be computed in about 0.88㎲ec at 50MHz clock frequency, resulting in the throughput rate of about 72 Mega pixels per second.
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Vector-radix 2차원 고속 DCT의 VLSI 구현을 위한 효율적인 어레이 알고리듬
신경욱,전흥우,강용섬 한국통신학회 1993 韓國通信學會論文誌 Vol.18 No.12
본 논문에서는 vector-radix 2차원 고속 DCT(VR-FCT)를 VLSI 병렬계산하기 위한 효율적인 어레이 알고리듬을 제안하고, 이를 집적회로로 구현하기 위한 회로를 설계하였다. VR-FCT 알고리듬의 버터플라이 연산부분을 2차원 어레이에 매핑하여 이를 병렬 및 파이프라인 처리함을써 VR-FCT 알고리듬의 고속성과 2차원 어레이의 병렬성 및 국부통신 특성을 동시에 이용할 수 있다는 특징을 갖는다. 제안된 구현방식은 RCA 방식과는 달리 transposition 메모리가 필요치 않으며, 2차원 어레이의 구조적인 규칙성, 모듈성 및 국부연결성 등에 의해 회로설계 시간의 단축, 설계검증 및 설계변경등이 용이하여 VLSI 구현에 매우 적합하다. 연산회로는 곱셈기를 사용하기않고 가산기만으로 설계하였으며, 2의 보수연산 대신에 Canonic-Signed Didit(CSD) 코드를 사용함으로써 약 30%의 가산횟수를 줄일 수 있었다. 제안된 방법의 DCT 연산과정을 C언어로 모델링하여 회로의 유한 레지스터 길이에 대한 연산정밀도를 분석하였다. 제안된 어레이 알고리듬의 시간성능은 (N*N) 2차원 DCT에 대해 O(N+Nnzd-log2N)의 시간 복잡도를 갖는다. 시뮬레이션 결과고부터 Nnzp=4이고 50MHz 클럭이 사용되는 경우, (8*8) DCT계산에 약 0.88 sec가 소요괴며, 약 72*10 pixels/sec의 연산성능이 예상된다. This paper describes an efficient array algorithm for parallel computation of vector-radix two-dimensional (2-D) fast discrete cosine transform (VR-FCT), and its VLSI implementation. By mapping the 2-D VR-FCT onto a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently importanted with high concurrency and local communication geometry. The proposed array algorithm features architectural modularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required, which is invitable in the conventional row-column decomposition approach. It has the time complexity of O(N+Nnzp-log2N) for (N*N) 2-D DCT, where Nnzd is the number of non-zero digits in canonic-signed digit(CSD) code, By adopting the CSD arithmetic in circuit desine, the number of addition is reduced by about 30%, as compared to the 2`s complement arithmetic. The computational accuracy analysis for finite wordlength processing is presented. From simulation result, it is estimated that (8*8) 2-D DCT (with Nnzp=4) can be computed in about 0.88 sec at 50 MHz clock frequency, resulting in the throughput rate of about 72 Mega pixels per second.
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박노경,차균현,이주석,김형곤,주병권,강용섬 대한전자공학회 1996 CAD 및 VLSI 설계연구회지 Vol.5 No.1
The proposed SRAM reusing charge operate in 3.3 voltage and we obtain 33.3% power save efficiency compared to the conventional wordline access method due to resuing the current of first actived wordline gate capacitance at second actived wordline gate capacitance. In the case of this SRAM reusing charge, described in this paper, we obtained 5ns(200MHz) operation speed result in the HYUNDAI 0.6um CMOS technology. In this paper power saving is 30.75mW compaired to the conventional wordline access for one clock.
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