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정연호,김동일,한상숙 청주대학교 산업과학연구소 1990 産業科學硏究 Vol.8 No.-
시성 데이타베이스는 시간 주기에 따라 실세계의 상태에 대한 데이터베이스에 있어서의 자료 변경은 새로운 정보의 추가를 의미하므로 대용량의 기억 장치가 요구된다. 본 논문에서는 논리적으로 자료의 양을 줄일 수 있는 방법으로 시간지원 데이타베이스에서 반드시 필요한 시간속성을 줄이는 방법을 제안한다. 시간속성은 실세계에서 일어나는 사건에 대한 시간이므로 중복이 발생되지 않는 유일한 값을 갖고 있다. 따라서 시간지원 데이터베이스의 접근방법 특징인 최근 버젼부터 과거버젼으로 접근하는 것을 이용하여 이력튜플에는 사건의 시작에 해당되는 하나의 속성으로 줄일 수 있게 한다.
정연호 청주대학교 산업과학연구소 1993 産業科學硏究 Vol.11 No.-
In this paper, the decoding scheme was studied by which reliable reproduction of information sequence can be accomplished from receiving sequence disturbed by the random error and the slippage of synchronization. The decoder was designed which consisted of error correction unit and synchronization recovery unit. It operates with the capability of combatting the disturbances. Having performed computer program for the decoding procedure, the results agreed with the theory.
정연호 청주대학교 산업과학연구소 1994 産業科學硏究 Vol.12 No.-
In this paper, A decoding system was studied which consisted of parallel coupling of two different decoders and an efficiently operated. Its one decoder consisted of an error correction unit and a synchronization recovery unit while the other decoder was only an error correction unit. The first received word can be designed to have either a synchronization field or both of a synchronization field and a classification field in its message area. The modulo-2 sum of the first received word and vector P is enter into the decoding system. The modulo-2 sum having passed through an error correction unit and a synchronization unit located at the upper decoder, one decoder was chosen between the two decoders according to the resultant output word such that the next modulo-2 sums could pass through it. One decoder was designed for triple-error-correcting (31,16) BCH code in addition.
정연호 청주대학교 산업과학연구소 1997 産業科學硏究 Vol.15 No.2
In recent Windows NT, I/O manager effectively controls the peripheral devices by the object-oriented programming(OOP). Any effectively managing technique that controls the peripheral devices by the OOP are not implemented easily, because they are protected from other applications by the Windows NT Kernel. This paper describes the PnP architecture in PCI environment for automatic recognition of peripheral devices and I/O process of Windows NT for peripheral devices.
鄭然湖 청주대학교 산업과학연구소 1989 産業科學硏究 Vol.7 No.-
In this paper, an application program for error correction was studied which based on the structure of the decoder and the decoding procedure for BCH code. Thus, the decoding for (63,51)BCH code was designed and then an application program was constructed correspondingly. By executing this application program for the different received vectors, it turned out that any error pattern nth two or fewer errors could be corrected.
순환 곱 부호를 사용한 파이프라인구조의 복호과정에 관한 연구
정연호 청주대학교 산업과학연구소 2005 産業科學硏究 Vol.23 No.1
In this paper, an efficient decoding technique with a pipeline version of the decoder for the cyclic product codes was studied. This decoding system is similar to a cascade decoder. But this decoding system differs from a cascade decoder because it has dual decoders as its column decoder as well as its row decoder and it has registers of rectangular array in the front and the bear of decoder. The decoding speed of a pipeline decoder was 3.2 times faster than that of a non-pipeline decoder with the same error correcting capability in the cyclic product codes which its row was (15,7) BCH code and its column was (7,4) BCH code. It was expected that the theoretical maximum decoding speedup which a pipeline decoder could provide was four.
鄭然湖 청주대학교 산업과학연구소 1988 産業科學硏究 Vol.6 No.-
A simple construction on the generator matrix of any cyclic code was studied in this paper. Its concept is based on the theory of an encoding circuit for any cyclic code. According to the theory, the generator matrix can be simply constructed without complex computation which has been essential to the previous construction on the generator matrix. Finally, the validity of the contents which were presented in this paper was verified by performing computer programs.
오류정정 시스템에서 사용되는 선형 스위칭 회로에 관한 연구
정연호 청주대학교 산업과학연구소 2003 産業科學硏究 Vol.21 No.1
Digital logic circuits can be easily organized into shift register circuit Shift register circuits can be used for the multiplication and division of polynomials over GF(2). These hear switching circuits are used frequently in design and construction of encoders and decoder. In this thesis, three man points of view were presented as follows. First, computations in polynomial algebras such as the multiplication and division of polynomials over GF(2). Second, application of shift register circuits such as circuits for multiplication or division of any polynomial by a fixed polynomial, two-input multiplier, a circuit for both multiplication and division of any polynomial by a fixed polynomial. Third, replacing diagram of shift register circuits by the register transfer statements. By many examples for the multiplication and division of polynomials over GF(2), it proved that the register transfer statements for the applications of shift register circuits were valuable in analysis.