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연산공유 승산 알고리즘을 이용한 내적의 최적화 및 이를 이용한 1차원 DCT 프로세서 설계
이태욱,조상복 대한전기학회 2004 전기학회논문지 D Vol.53 No.2(D)
The DCT algorithm needs an efficient hardware architecture to compute inner product. The conventional design method, like ROM-based DA(Distributed Arithmetic), has large hardware complexity. Because of this reason, a CSHM(Computation SHaring Multiplication) was proposed for implementing inner product by Park. However, the Park's CSHM has inefficient hardware architecture in the precomputer and select units. Therefore it degrades the performance of the multiplier. In this paper, we presents the optimization design method for inner product using CSHM algorithm and applied it to implementation of 1-D DCT processor. The experimental results show that the proposed multiplier is more efficient than Park's when hardware architectures and logic synthesis results were compared. The designed 1-D DCT processor by using proposed design method is more high performance than typical methods.
이태욱,조상복,Lee, Tae-Uk,Jo, Sang-Bok 대한전자공학회 2000 電子工學會論文誌-SD (Semiconductor and devices) Vol.37 No.5
본 논문에서는 CPF(Carry-Propagation-Free)의 특성을 갖는 RB(Redundant Binary)연산을 이용한 새로운 구조의 24비트 2의 보수 덧셈기를 설계하였다. TC2RB(Two's Complement to RB SUM converter)의 속도와 트랜지스터 개수를 줄이기 위해 MPPL(Modifed PPL) XOR/XNOR 게이트를 제안하고 고속 RB2TC(RB SUM to Two's Complement converter)를 사용한 두 가지 형태의 덧셈기를 제안하였다. 각 덧셈기의 특징을 살펴보면, TYPE 1 덧셈기는 VGS(Variable Group Select) 방식을 사용하여 덧셈기의 속도를 향상시켰으며 TYPE 2 덧셈기는 64비트 GCG(Group Change bit Generator)회로와 8비트 TYPE 1 덧셈기를 사용하여 속도를 향상시켰다. 64비트 TYPE 1 덧셈기의 경우 CLA와 CSA에 비해 각각 23.5%, 29.7%의 속도 향상을 TYPE 2 덧셈기의 경우 각각 41.2%, 45.9%의 속도 향상을 기대할 수 있다. 레이아웃된 24비트 TYPE 1과 TYPE 2 덧셈기의 전달지연 시간은 각각 1.4ns와 1.2ns로 나왔다. 제안한 덧셈기는 매우 규칙적인 구조를 가지고 있기 때문에 빠른 시간에 회로 설계 및 레이아웃이 가능하며 마이크로프로세서나 DSP 등과 같이 고속연산을 필요로 하는 경우에 적합하다. In this paper a new architecture of 24-bit two's complement adder is designed by using RB(Redundant Binary) arithmetic which has the advantage of CPF(Carry-Propagation-Free). A MPPL(Modified PPL) XOR/XNOR gate is applied to improve a TC2RB(Two's Complement to RB SUM converter) speed and to reduce the number of transistors, and we proposed two types adder which used a fast RB2TC(RB SUM to Two's Complement converter). The property of two types adder is followings. The improvement of TYPE 1 adder speed is archived through the use of VGS(Variable Group Select) method and TYPE 2 adder is through the use of a 64-bit GCG(Group Change bit Generator) circuit and a 8-bit TYPE 1 adder. For 64-bit, TYPE 1 adder can be expected speed improvement of 23.5%, 25.7% comparing with the CLA and CSA, and TYPE 2 adder can be expected 41.2%, 45.9% respectively. The propagation delay of designed 24-bit TYPE 1 adder is 1.4ns and TYPE 2 adder is 1.2ns. The implementation is highly regular with repeated modules and is very well suited for microprocessor systems and fast DSP units.
비트 레벨 정렬 알고리즘을 이용한 3×3 윈도우 가중 메디언 필터의 하드웨어 구현에 관한 연구
이태욱,조상복 대한전기학회 2004 전기학회논문지 D Vol.53 No.3(D)
In this paper, we studied on the hardware implementation of a 3×3 window weighted median filter using bit-level sorting algorithm. The weighted median filter is a generalization of the median filter that is able to preserve sharp changes in signal and is very effective in removing impulse noise. It has been successfully applied in various areas such as digital signal and video/image processing. The weighted median filters are, for the most part, based on word-level sorting methods, which have more hardware and time complexity. However, the proposed bit-serial sorting algorithm uses weighted adder tree to overcome those disadvantages. It also offers a simple pipelined filter architecture that is highly regular with repeated modules and is very suitable for weighted median filtering. The algorithm was implemented by VHDL and graphical environment in MAX+PlusII of ALTERA. The simulation results indicate that the proposed design method is more efficient than the traditional ones.
Analysis of Korean Patent Information for Air Extraction Cupping Devices
이태욱,Ku Weon Kim,김효진,최지원,최서영,이병렬,양기영 대한침구의학회 2019 대한침구의학회지 Vol.36 No.1
Background: The purpose of this study was to collate inventors’ improvements of air extraction cupping technology by reviewing patent applications in Korea. The cost of procurement and use of air extraction cupping devices are covered by health insurance. Methods: Patents registered in Korea for air extraction cupping devices from August 1992 to January 2018 (registration, expiration, rejection, abandonment, and disclosure) were analyzed to determine technology trends. The Korean patent search engine used was Kipris (www.kipris.or.kr). Results: Sixty-seven Korean patents for air extraction cupping devices were retrieved. Most patents focused on design of the top valve of the device, the device at the bottom, an internal device, and the disposable cupping glass. In total 17.9% of patents were registered and 64.2% were abolished [either from non-payment of registration fees (93%) or expiration of the patent after 10 years (7%)]. The average registration period was 3.7 years. Conclusion: The patents retrieved for this study focused on the development of the air exhaust valve, disposable cups, and skin adhesion maintenance technology in cupping devices that use air extraction. The average registration period was 3.7 years, meaning the patents that were not commercialized, expired without additional registration renewals. It is important to acquire a New Excellent Technology certificate for a cupping device to promote commercialization.