실리콘 웨이퍼의 비유전율과 손실 탄젠트의 측정

이원희 한국지식정보기술학회 2022 한국지식정보기술학회 논문지 Vol.17 No.1

The operating frequency of designed circuits on silicon wafers is expanding from the microwave band to the millimeter wave band. When a circuit is constructed using a silicon wafer, the operating frequency and high-frequency harmonics must be considered. Therefore, it is possible to accurately design a circuit that it is necessary to know exactly the relative permittivity and loss tangent of silicon wafers. In this paper, the relative permittivity and loss tangent of a silicon waver were measured using a cylindrical cavity resonator. In the case of a silicon wafer, it is easily broken, so it is impossible to measure it using the conventional the relative permittivity and loss tangent measurement methods. However, when measured by the method of this paper, it is possible to measure after breaking a silicon wafer and inserting it into a cylindrical cavity resonator, so it is easy to measure. The relative permittivity and loss tangent of the silicon wafer on the simulator were measured by selecting the mode with the largest change in the resonance frequency. This is results in the case of inserting the silicon wafer into the cylindrical cavity resonator and in the case of empty. As a results of the measurement, in the case of the silicon wafer doped with AS, the relative permittivity was high at 16.5 and the loss tangent was high as 0.5. In the case of a silicon wafer with a resistivity of 19, the relative permittivity was 12 and the loss tangent was 0.1.

Automated Wafer Separation from the Stacked Array of Solar Cell Silicon Wafers Using Continuous Water Jet

곽호상,김경진,김동주 한국반도체디스플레이기술학회 2010 반도체디스플레이기술학회지 Vol.9 No.2

In response to the industrial needs for automated handling of very thin solar cell wafers, this paper presents the design concept for the individual wafer separation from the stacked wafers by utilizing continuous water jet. The experimental apparatus for automated wafer separation was constructed and it includes the water jet system and the microprocessor controlled wafer stack advancing system. Through a series of tests, the performance of the proposed design is quantified into the success rate of single wafer separation and the rapidity of processing wafer stack. Also, the inclination angle of wafer equipped cartridge and the water jet flowrate are found to be important parameters to be considered for process optimization. The proposed design shows the concept for fast and efficient processing of wafer separation and can be implemented in the automated manufacturing of silicon based solar cell wafers.

실리콘 웨이퍼 연마헤드의 강제구동 방식이 웨이퍼 연마 평탄도에 미치는 영향 연구

김경진,박중윤 한국반도체디스플레이기술학회 2014 반도체디스플레이기술학회지 Vol.13 No.1

Since the semiconductor manufacturing requires the silicon wafers with extraordinary degree of surface flatness, the surface polishing of wafers from ingot cutting is an important process for deciding surface quality of wafers. The present study introduces the development of wafer polishing equipment and, especially, the wafer polishing head that employs the forced self-driving of installed silicon wafer as well as the wax wafer mounting technique. A series of wafer polishing tests have been carried out to investigate the effects of self-driving function in wafer polishing head. The test results for wafer planarization showed that the LLS counts and SBIR of polished wafer surfaces were generally improved by adopting the self-driven polishing head in wafer polishing stations.

A Highly Sensitive Determination of Bulk Cu and Ni in Heavily Boron-doped Silicon Wafers

Lee, Sung-Wook,Lee, Sang-Hak,Kim, Young-Hoon,Kim, Ja-Young,Hwang, Don-Ha,Lee, Bo-Young Korean Chemical Society 2011 Bulletin of the Korean Chemical Society Vol.32 No.7

The new metrology, Advanced Poly-silicon Ultra-Trace Profiling (APUTP), was developed for measuring bulk Cu and Ni in heavily boron-doped silicon wafers. A Ni recovery yield of 98.8% and a Cu recovery yield of 96.0% were achieved by optimizing the vapor phase etching and the wafer surface scanning conditions, following capture of Cu and Ni by the poly-silicon layer. A lower limit of detection (LOD) than previous techniques could be achieved using the mixture vapor etching method. This method can be used to indicate the amount of Cu and Ni resulting from bulk contamination in heavily boron-doped silicon wafers during wafer manufacturing. It was found that a higher degree of bulk Ni contamination arose during alkaline etching of heavily boron-doped silicon wafers compared with lightly boron-doped silicon wafers. In addition, it was proven that bulk Cu contamination was easily introduced in the heavily boron-doped silicon wafer by polishing the wafer with a slurry containing Cu in the presence of amine additives.

A Highly Sensitive Determination of Bulk Cu and Ni in Heavily Boron-doped Silicon Wafers

Sung-wook Lee,Sang-hak Lee,Young-hoon Kim,Ja-young Kim,Don-ha Hwang,Bo-young Lee 대한화학회 2011 Bulletin of the Korean Chemical Society Vol.32 No.7

The new metrology, Advanced Poly-silicon Ultra-Trace Profiling (APUTP), was developed for measuring bulk Cu and Ni in heavily boron-doped silicon wafers. A Ni recovery yield of 98.8% and a Cu recovery yield of 96.0% were achieved by optimizing the vapor phase etching and the wafer surface scanning conditions,following capture of Cu and Ni by the poly-silicon layer. A lower limit of detection (LOD) than previous techniques could be achieved using the mixture vapor etching method. This method can be used to indicate the amount of Cu and Ni resulting from bulk contamination in heavily boron-doped silicon wafers during wafer manufacturing. It was found that a higher degree of bulk Ni contamination arose during alkaline etching of heavily boron-doped silicon wafers compared with lightly boron-doped silicon wafers. In addition, it was proven that bulk Cu contamination was easily introduced in the heavily boron-doped silicon wafer by polishing the wafer with a slurry containing Cu in the presence of amine additives.

Automated Wafer Separation from the Stacked Array of Solar Cell Silicon Wafers Using Continuous Water Jet

Kim, Kyoung-Jin,Kim, Dong-Joo,Kwak, Ho-Sang The Korean Society Of SemiconductorDisplay Technol 2010 반도체디스플레이기술학회지 Vol.9 No.2

In response to the industrial needs for automated handling of very thin solar cell wafers, this paper presents the design concept for the individual wafer separation from the stacked wafers by utilizing continuous water jet. The experimental apparatus for automated wafer separation was constructed and it includes the water jet system and the microprocessor controlled wafer stack advancing system. Through a series of tests, the performance of the proposed design is quantified into the success rate of single wafer separation and the rapidity of processing wafer stack. Also, the inclination angle of wafer equipped cartridge and the water jet flowrate are found to be important parameters to be considered for process optimization. The proposed design shows the concept for fast and efficient processing of wafer separation and can be implemented in the automated manufacturing of silicon based solar cell wafers.

SOI 웨이퍼를 이용한 Top emission 방식 AMOLEDs의 스위칭 소자용 단결정 실리콘 트랜지스터

장재원,김훈,신경식,김재경,주병권,Chang, Jae-Won,Kim, Hoon,Shin, Kyeong-Sik,Kim, Jai-Kyeong,Ju, Byeong-Kwon 한국전기전자재료학회 2003 전기전자재료학회논문지 Vol.16 No.4

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

다결정 실리콘 웨이퍼 직접제조에 대한 공정변수 영향

위성민 ( Sung Min Wi ),이진석 ( Jin Seok Lee ),장보윤 ( Bo Yun Jang ),김준수 ( Joon Soo Kim ),안영수 ( Young Soo Ahn ),윤우영 ( Woo Young Yoon ) 한국주조공학회 2013 한국주조공학회지 Vol.33 No.4

A ribbon-type polycrystalline silicon wafer was directly fabricated from liquid silicon via a novel technique for both a fast growth rate and lagre grain size by exploiting gas pressure. Effects of processing parameters such as moving speed of a dummy bar and the length of the solidification zone on continuous casting of the silicon wafer were investigated. Silicon melt extruded from the growth region in the case of a solidification zone with a length of lcm due to incomplete solidification. In case of a solidification zone wieh a length fo 2 cm, on the other hand, continuous casting of the wafer was impossible due to the volume expansion of sil-icon derived from the liquid-solid transformation in solidificatioon zone. Consequently, the optimal length of the solidification zone was 1.5 cm for maintaining the position of the dummy bar was 6 cm/min, but liquid silicon extruded from the growth region without solidification when the moving speed of the dummy barr was≥9 cm/min. This was due to a shift of the position of the solid-liquid interface from the solidification zone to the moving area. The present study repots experimental findings on a new direct growth sys-tem for obtaining silicon wafers with both high quality and producticity, as a candidate for an altemate route for the fabrication of ribbon-type silicon wafers.

열처리 온도에 따른 니켈실리사이드 실리콘 기판쌍의 직접접합

송오성,안영숙,이영민,양철웅,Song, O-Seong,An, Yeong-Suk,Lee, Yeong-Min,Yang, Cheol-Ung 한국재료학회 2001 한국재료학회지 Vol.11 No.7

실리사이드반웅을 이용하여 니켈모노실리사이드의 양측계면에 단결정실리콘을 적층시켜 전도성이 우수하며 식각특성이 달라 MEMS용 기판으로 채용이 가능한 SOS (Silicon-on-Silicide) 기판을 제작하였다. 실리콘 기판 전면에 Ni를 열증착법으로$ 1000\AA$두께로 성막하고, 실리콘 기판 경면과 맞블여 후 $300~900^{\circ}C$온도범위에서 15시간동안 실리사이드 처리하여 니켈모노실리사이드가 접합매체로 되는 기판쌍들을 완성하였다. 완성된 기판쌍들은 IR (infrared) 카메라를 이용하여 비파괴적으로 접합상태를 확인하고. 주사전자현미경 (scaning electron microscope)과 투과전자현미경 (tranmission electron microscope)을 이용하여 수직단면 미세구조를 확인하였다. Ni 실리사이드의 상변화가 일어나는 온도를 제외하고는 Si NiSi ∥Si 기판쌍은 기판전면에 52%이상 완전접합이 진행되었음을 확인하였고 생성 실리사이드의 두께에 따라 나타나는 명암부에 비추어 기판쌍 중앙부에 두꺼운 니켈노실리아드가 형성되었다고 판단되었다. 완성된 Si NiSi ∥ Si 기판쌍을 SBM 수직단면에 의괘 확인한 결과 접합이 완성된 기판중심부의 접합계면은 $1000\AA$ 두께의 NiSi가 균일하게 형성되었으며 배율 30,000배의 해상도에서 계면간 분리부분없이 완전한 접합이 진행되었음을 확인하였다. 반면 기판쌍 에지 (edge)부분에는 실리사이드가 헝성되지 않은 비접합상태가 발견되었다. 수직단면루과전자현미경 결과물에 근거하여 접합된 중심부에서는 피접합되는 실리콘의 경면과 니켈이 성막된 실리콘 경면 상부계면에 10-20$\AA$의 비정질막이 발견되었으며, 산화막으로 추정되는 이 막이 접합률을 현저히 저하시키는 것을 확인하였다. 접합이 진행되지 않은 에지부는 이러한 산화막이 열처리 진행중 급격히 성장하여 피접합 실리콘층의 분리가 발생하였다. 따라서 Si NiSi ∥Si 기판쌍의 접합률을 향상시키기 위해서는 피접합 실리콘 계면과 Ni 상부층간의 비정질부를 적극적으로 제거하여야 함을 알 수 있었다. We prepared a new a SOS(silicon-on-silicide) wafer pair which is consisted of Si(100)/1000$\AA$-NiSi Si (100) layers. SOS can be employed in MEMS(micro- electronic-mechanical system) application due to low resistance of the NiSi layer. A thermally evaporated $1000\AA$-thick Ni/Si wafer and a clean Si wafer were pre-mated in the class 100 clean room, then annealed at $300~900^{\circ}C$ for 15hrs to induce silicidation reaction. SOS wafer pairs were investigated by a IR camera to measure bonded area and probed by a SEM(scanning electron microscope) and TEM(transmission electron microscope) to observe cross-sectional view of Si/NiSi. IR camera observation showed that the annealed SOS wafer pairs have over 52% bonded area in all temperature region except silicidation phase transition temperature. By probing cross-sectional view with SEM of magnification of 30,000, we found that $1000\AA$-thick uniform NiSi layer was formed at the center area of bonded wafers without void defects. However we observed debonded area at the edge area of wafers. Through TEM observation, we found that $10-20\AA$ thick amourphous layer formed between Si surface and NiSix near the counter part of SOS. This layer may be an oxide layer and lead to degradation of bonding. At the edge area of wafers, that amorphous layer was formed even to thickness of $1500\AA$ during annealing. Therefore, to increase bonding area of Si NiSi ∥ Si wafer pairs, we may lessen the amorphous layers.

An Emissivity-Invariant Condition of Silicon Wafers and Its Application to Radiation Thermometry

Tohru Iuchi,Atsushi Gogami 제어로봇시스템학회 2009 제어로봇시스템학회 국제학술대회 논문집 Vol.2009 No.8

The emissivity behavior of a silicon wafer is simulated using a simple modeling of the spectral, directionaland polarization characteristics of thermal radiation. This study reveals that the p-polarized spectral emissivity of the silicon wafer at a specified direction remains constant. Then, subsequent experiments confirmed the simulated resultsthat the p-polarized emissivity of silicon wafers is maintained to be 0.83 at an angle of 55.4º and a wavelength of 0.9 μm in spite of wide variations in oxide film thickness from 0 to 950 nm, temperature over 900 K as well as resistivity from0.01 to 2000 Ωcm relevant to impurity concentrations doped into the silicon wafer. The overall extended uncertainty (k=2) of the temperature measurement is estimated to be 3.82 K over 900 K at the moment. This result is expected to enable significantly more accurate in situ radiation thermometry of silicon wafers in real manufacturing processes.