A High-Isolation MIMO Antenna with Dual-Port Structure for 5G Mobile Phones

( Hyung-kyu Yang ),( Won-woo Lee ),( Byung-ho Rhee ) 한국인터넷정보학회 2018 KSII Transactions on Internet and Information Syst Vol.12 No.4

In this letter, a new dual-port Multiple-Input Multiple-Output (MIMO) antenna is introduced which has two independent signal feeding ports in a single antenna element to achieve smaller antenna volumes for the 5G mobile applications. The dual-port structure is implemented by adding a cross coupled semi-loop (CCSL) antenna as the secondary radiator to the ground short of inverted-F antenna (IFA). It is found that the port to port isolation is not deteriorated when an IFA and CCSL is combined to form a dual-port structure. The isolation property of the proposed antenna is compared with a polarization diversity based dual-port antenna proposed in the literature [9]. The operating frequency range is 3.3-4.0 GHz which is suitable for places where 4x4 MIMO systems are supposed to be deployed such as in China, EU, Korea and Japan at the band x (3.3 - 3.8GHz. The measured 6-dB impedance bandwidths of the proposed antennas are larger than 700 MHz with isolation between the feeding ports higher than 18 dB [1-2]. The simulation and measurement results show that the proposed antenna concept is a very promising alternative for 5G mobile applications.

Three-Port Converters with a Flexible Power Flow for Integrating PV and Energy Storage into a DC Bus

Tian Cheng,Dylan Dah-Chuan Lu 전력전자학회 2017 JOURNAL OF POWER ELECTRONICS Vol.17 No.6

A family of non-isolated DC-DC three-port converters (TPCs) that allows for a more flexible power flow among a renewable energy source, an energy storage device and a current-reversible DC bus is introduced. Most of the reported non-isolated topologies in this area consider only a power consuming load. However, for applications such as hybrid-electric vehicle braking systems and DC microgrids, the load power generating capability should also be considered. The proposed three-port family consists of one unidirectional port and two bi-directional ports. Hence, they are well-suited for photovoltaic (PV)-battery-DC bus systems from the power flow viewpoint. Three-port converters are derived by combining different commonly known power converters in an integrated manner while considering the voltage polarity, voltage levels among the ports and the overall voltage conversion ratio. The derived converter topologies are able to allow for seven different modes of operation among the sources and load. A three-port converter which integrates a boost converter with a buck converter is used as a design example. Extensions of these topologies by combining the soft-switching technique with the proposed design example are also presented. Experiment results are given to verify the proposed three-port converter family and its analysis.

Software Defined Radio를 위한 I/Q 부정합 보정 기능을 갖는 이중 대역 Six-Port 직접변환 수신기

문성모(Seong-Mo Moon),박동훈(Donghoon Park),유종원(Jong-Won Yu),이문규(Moon-Que Lee) 한국전자파학회 2010 한국전자파학회논문지 Vol.21 No.6

본 논문에서는 software defined radio(SDR) 기반의 고속의 다중 모드, 다중 대역을 위한 새로운 six-port 직접변환 수신기를 제안한다. 설계한 수신기는 2개의 CMOS four-port BPSK 수신기와 직교 LO 신호 발생을 위한 이중 대역 1단 polyphase 필터로 구성되어 있다. 0.18 ㎛ CMOS 공정을 이용하여 마이크로파 대역에서 처음으로 개발한 four-port 수신기는 두 개의 능동 결합기, 능동 발룬, 두 개의 전력 검출기 및 아날로그 디코더로 구현되어 있다. 제안한 polyphase 필터는 type-I 구조를 선택하였으며, LO 신호의 전력 손실을 줄이기 위하여 1단으로 구현 하였고, 커패시터를 사용하는 것 대신하여 LC 공진구조를 적용하여 이중 대역 동작을 구현하였다. 제안한 sixport 수신기의 RF 가용범위를 확장하기 위하여, six-port junction과 전력 검출기에 I/Q 위상 및 크기를 보정하는 회로를 추가하였다. 제안한 회로에서 위상과 크기 부정합의 보정 범위는 각각 8도와 14 dB이다. 제작한 six-port 수신기는 이중 대역인 900 MHz와 2.4 ㎓ 대역에서 M-QAM, M-PSK의 40 Msps의 변조 신호를 성공적으로 복조하였다. In this paper, a new six-port direct conversion receiver for high-speed multi-band multi-mode wireless communication system such as software defined radio(SDR) is proposed. The designed receiver is composed of two CMOS four-port BPSK receivers and a dual-band one-stage polyphase filter for quadrature LO signal generation. The four-port BPSK receiver, implemented in 0.18 ㎛ CMOS technology for the first time in microwave-band, is composed of two active combiners, an active balun, two power detector, and an analog decoder. The proposed polyphase filter adopt type-I architecture, one-stage for reduction of the local oscillator power loss, and LC resonance structure instead of using capacitor for dual-band operation. In order to extent the operation RF bandwidth of the proposed six-port receiver, we include I/Q phase and amplitude calibration scheme in the six-port junction and the power detector. The calibration range of the phase and amplitude mismatch in the proposed calibration scheme is 8 degree and 14 ㏈, respectively. The validity of the designed six-port receiver is successfully demonstrated by modulating M-QAM, and M-PSK signal with 40 Msps in the two-band of 900 ㎒ and 2.4 ㎓.

디스플레이 IC 내장형 Dual-Port 1T-SRAM를 위한 간단한 시프트 로직 회로를 이용한 데이터라인 리던던시 회로

권오삼,민경식,Kwon, O-Sam,Min, Kyeong-Sik 한국전기전자학회 2007 전기전자학회논문지 Vol.11 No.4

본 논문에서는 Dual-Port 구조를 사용하는 Display IC용 내장형 1T-SRAM에 적합한 간단하고 효과적인 새로운 데이터라인 리던던시 회로(dataline redundancy circuit)를 제안하고 이를 0.18-um CMOS 1T-SRAM 공정을 이용하여 $320{\times}120{\times}18$-Bit Dual-port 1T-SRAM로 구현하여 검증하였다. 한 개의 인버터와 한 개의 낸드 게이트로 이루어진 시프트 로직 회로(shift logic circuit)를 이용해서 기존의 데이터라인 리던던시 회로 보다는 훨씬 간단하게 컨트롤 로직을 구현함으로써 한 개의 비트라인 페어(bit line pair)의 피치(pitch) 내에서 필요한 컨트롤 로직을 모두 구현할 수 있었다. 또한 시프트 로직 회로를 개선해서 worst case에서의 delay를 12.3ns에서 5.9ns로 52% 감소시켜서 워드라인 셋업 후에서 센스앰프 셋업까지의 시간 동안에 데이터라인 스위칭 작업을 완료할 수 있게 하여서 데이터라인 리던던시 회로의 타이밍 오버헤드(timing overhead)를 row cycle 시간에 의해 감추어지게 할 수 있었다. 본 논문에서 제시된 데이터라인 리던던시 회로의 면적 오버헤드(area overhead)는 약 7.6%로 예측된다. In this paper, a simple but effective Dataline Redundancy Circuit (DRC) is proposed for a dual-port 1T-SRAM embedded in Display ICs. The DRC designed in the dual-port $320{\times}120{\times}18$-bit 1T-SRAM is verified in a 0.18-um CMOS 1T-SRAM process. In the DRC, because its control logic circuit can be implemented by a simple Shift Logic Circuit (SLC) with only an inverter and a NAND that is much simpler than the conventional, it can be placed in a pitch as narrow as a bit line pair. Moreover, an improved version of the SLC is also proposed to reduce its worst-case delay from 12.3ns to 5.9ns by 52%. By doing so, the timing overhead of the DRC can be hidden under the row cycle time because switching of the datalines can be done between the times of the word line setup and the sense amplifier setup. The area overhead of the DRC is estimated about 7.6% in this paper.

Three-Port Converters with a Flexible Power Flow for Integrating PV and Energy Storage into a DC Bus

Cheng, Tian,Lu, Dylan Dah-Chuan The Korean Institute of Power Electronics 2017 JOURNAL OF POWER ELECTRONICS Vol.17 No.6

A family of non-isolated DC-DC three-port converters (TPCs) that allows for a more flexible power flow among a renewable energy source, an energy storage device and a current-reversible DC bus is introduced. Most of the reported non-isolated topologies in this area consider only a power consuming load. However, for applications such as hybrid-electric vehicle braking systems and DC microgrids, the load power generating capability should also be considered. The proposed three-port family consists of one unidirectional port and two bi-directional ports. Hence, they are well-suited for photovoltaic (PV)-battery-DC bus systems from the power flow viewpoint. Three-port converters are derived by combining different commonly known power converters in an integrated manner while considering the voltage polarity, voltage levels among the ports and the overall voltage conversion ratio. The derived converter topologies are able to allow for seven different modes of operation among the sources and load. A three-port converter which integrates a boost converter with a buck converter is used as a design example. Extensions of these topologies by combining the soft-switching technique with the proposed design example are also presented. Experiment results are given to verify the proposed three-port converter family and its analysis.

Dual-Port SDRAM Optimization with Semaphore Authority Management Controller

Jaehwan Kim,정정화 한국전자통신연구원 2010 ETRI Journal Vol.32 No.1

This paper proposes the semaphore authority management (SAM) controller to optimize the dual-port SDRAM (DPSDRAM) in the mobile multimedia systems. Recently, the DPSDRAM with a shared bank enabling the exchange of data between two processors at high speed has been developed for mobile multimedia systems based on dual-processors. However, the latency of DPSDRAM caused by the semaphore for preventing the access contention at the shared bank slows down the data transfer rate and reduces the memory bandwidth. The methodology of SAM increases the data transfer rate by minimizing the semaphore latency. The SAM prevents the latency of reading the semaphore register of DPSDRAM, and reduces the latency of waiting for the authority of the shared bank to be changed. It also reduces the number of authority requests and the number of times authority changes. The experimental results using a 1 Gb DPSDRAM (OneDRAM) with the SAM controllers at 66 MHz show 1.6 times improvement of the data transfer rate between two processors compared with the traditional controller. In addition, the SAM shows bandwidth enhancement of up to 38% for port A and 31% for port B compared with the traditional controller.

CFD 및 GT-Power 해석을 이용한 가솔린 Dual-Injector 엔진의 성능 개선에 관한 연구

김충식(Choongsik Kim),홍순성(Soonseong Hong),이재욱(Jaewook Lee) 한국자동차공학회 2014 한국자동차공학회 부문종합 학술대회 Vol.2014 No.5

Optimal intake system design for a dual-injector PFI (Port Fuel Injection) application was studied by using CFD analysis and the performance improvement was predicted by GT-Power analysis. Dual-injector PFI system provides better charge cooling and combustion stability which makes it possible to achieve engine performance and fuel efficiency improvement on conventional MPFI system. Since fuel injection system change from a conventional PFI to a dual-injector system was tried in this study, intake manifold and ports designs also should be changed to incorporate the dual-injector system and to maximize the performance and fuel efficiency gain. A number of intake port design variants were evaluated by using CFD from tumble and flow capacity perspectives and the intake manifold design was proposed to fit the selected port design. As intake system design was decided, engine performance simulation was carried out to project engine performance improvement with dual-injector based engine hardware. From the series of development activities, dyno test showed engine torque increase especially at low engine speeds and BSFC improvement at key part load conditions.

Numerical study of the effects of injection-port design on the heating performance of an R134a heat pump with vapor injection used in electric vehicles

Jung, Jongho,Jeon, Yongseok,Lee, Hoseong,Kim, Yongchan Pergamon 2017 Applied thermal engineering Vol. No.

<P><B>Abstract</B></P> <P>Heat pumps, which enable the cooling and heating of vehicular cabins, consume a significant portion of the total energy consumption in electric vehicles (EVs). The efficiency of the heat pump is typically degraded owing to cold-weather conditions, so the refrigerant-injection technique has been proposed for improving the system performance and compressor reliability. In this study, a simulation model for an R134a heat pump with vapor injection is developed and validated by performing thermodynamic analyses with geometrical information. The effects of the injection-port design are investigated using the developed numerical model. Single-injection and dual-injection ports are considered to optimize the coefficient of performance (COP) and isentropic efficiency by controlling the injection mass flow rate. The optimal angles of the single- and dual-injection ports are determined to be 440° and 535°/355° (for pocket A/B), respectively, while the corresponding COPs are improved by 7.5% and 9.8%, respectively, compared to the non-injection heat pump at an outdoor temperature of −10°C.</P> <P><B>Highlights</B></P> <P> <UL> <LI> A simulation model for an EV heat pump with vapor injection is developed and validated. </LI> <LI> Geometries of the injection port are analyzed according to angle of the injection port. </LI> <LI> Design of the injection port is determined to optimize COP and isentropic efficiency. </LI> <LI> Performance of dual-injection ports is compared to that of the non-injection heat pump. </LI> </UL> </P>

Dual Injection System 을 적용한 포트 분사 방식 가솔린 엔진의 냉간 시동 특성에 대한 연구

이준순 ( Junsun Lee ),김정환 ( Junghwan Kim ),오승묵 ( Seungmook Oh ),이용규 ( Yonggyu Lee ) 한국액체미립화학회 2016 한국액체미립화학회 학술강연회 논문집 Vol.2016 No.-

In the port fuel injection (PFI) system, fuel and air are mixed in the intake port and then introduced into the engine cylinder. While a typical injector setup for conventional PFI engines is one injector per cylinder, the dual port injection (DPI) system employs two injectors per cylinder. One advantage of having two injectors is that the two PFI injectors can locate closer to the intake valves so that their fuel spray can directly target the back of the intake valves. On the other hand, the conventional PFI system is required to locate the injector prior to the intake port split for equal fuel distribution between the two intake ports. This DPI configuration could reduce wall-wetting leading to total hydrocarbon (THC) reduction. In the present study, 5 DPI configurations varying in the fuel spray and installation were investigated under the cold-start experiment using a 1.6 liter, spark-ignition, gasoline engine. The results showed that the DPI system achieved significant THC reduction and marginal fuel economy improvement in the cold-start operation in comparison to the conventional PFI system.

Dual-port SDRAM Architecture for Low-power Communication of Internet-of-things Devices

Sungchan Kim,Hoeseok Yang 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.6

In this paper, we propose a dual-port SDRAM architecture as an energy-efficient inter-processor communication solution tailored to Internet-of-Things (IoTs) devices. Since a single memory chip plays the role of the local memories and the shared memory for both processors, it gives a simpler solution than a typical architecture that uses an additional dual-port SRAM as shared memory. To minimize the non-negligible synchronization overhead, we also propose two optimization techniques by exploiting the communication patterns of a target application: lock-priority and static-copy. Experiments on a virtual prototyping system show promising results, in which we achieved about 25-50% performance gain as well as about 40% power saving from the proposed optimization techniques compared with the existing architecture.