Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design

Shin, SangHak,Choi, Jun-Myung,Cho, Seongik,Min, Kyeong-Sik Springer 2013 NANOSCALE RESEARCH LETTERS Vol.8 No.1

<P>In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.</P>

CMOS-Memristor Hybrid 4-bit Multiplier Circuit for Energy-Efficient Computing

Vo, Huan Minh,Truong, Son Ngoc,Shin, Sanghak,Min, Kyeong-Sik Institute of Korean Electrical and Electronics Eng 2014 전기전자학회논문지 Vol.18 No.2

In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as $4F^2$.

CMOS-Memristor Hybrid 4-bit Multiplier Circuit for Energy-Efficient Computing

Huan Minh Vo,Son Ngoc Truong,신상학,민경식 한국전기전자학회 2014 전기전자학회논문지 Vol.18 No.2

In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as 4F2.

A novel fabrication method for co-integrating ISFET with damage-free sensing oxide and threshold voltage-tunable CMOS read-out circuits

Kwon, Dae Woong,Lee, Ryoongbin,Kim, Sihyun,Mo, Hyun-Sun,Kim, Dae Hwan,Park, Byung-Gook Elsevier 2018 Sensors and actuators. B Chemical Vol.260 No.-

<P><B>Abstract</B></P> <P>A novel fabrication method using a top SiO<SUB>2</SUB>-SiN-bottom SiO<SUB>2</SUB> (ONO) dielectric stack is proposed and implemented to obtain ion sensitive field effect transistor (ISFET) with damage-free sensing oxide and threshold voltage (<I>V</I> <SUB>th</SUB>)-tunable devices in CMOS read-out circuits. By wet-etching the top SiO<SUB>2</SUB> and the SiN sequentially, the ISFET with damage-free sensing oxide is obtained due to the high selectivity between them. Also, the <I>V</I> <SUB>th</SUB>-tunable circuit devices with the ONO stacks are simultaneously achieved by protecting the ONO stacks from the wet-etching. Through the measurements of pH and biomolecule responses, it is confirmed that the pH and biomolecule can be detected stably because the drain current (<I>I</I> <SUB>D</SUB>) is stabilized to a predetermined value more quickly and the <I>I</I> <SUB>D</SUB> fluctuation during the <I>I</I> <SUB>D</SUB> stabilization is significantly reduced compared with devices having damaged sensing oxide. Additionally, it is verified that the <I>V</I> <SUB>th</SUB> of devices for circuits can be fine-controlled by injecting charges into the SiN via Fowler-Nordheim tunneling. Furthermore, it is demonstrated that the biomolecule-induced <I>V</I> <SUB>th</SUB> shift of ∼150 mV in the proposed ISFET is successfully amplified to the output voltage change of ∼370 mV in common source amplifier (CSA) voltage-readout circuit consisting of one p-type ISFET and one <I>V</I> <SUB>th</SUB>-tuned n-type MOS.</P> <P><B>Highlights</B></P> <P> <UL> <LI> The damage-free sensing oxide is obtained using top SiO<SUB>2</SUB>-SiN-bottom SiO<SUB>2</SUB> (ONO) dielectric stack in the proposed ISFET. </LI> <LI> The drift and fluctuation of the drain current are significantly reduced by the damage-free sensing oxide. </LI> <LI> The threshold voltage (<I>V</I> <SUB>th</SUB>)-tunable CMOS read-out circuits are simultaneously obtained with the ISFET by using the ONO stack. </LI> <LI> The biomolecule sensing system consisting of the proposed ISFET and <I>V</I> <SUB>th</SUB>-tunable CMOS read-out circuits is demonstrated. </LI> </UL> </P>

A Simple Technique to Improve the Output Voltage of the CMOS Dickson Charge Pump Circuit

Jirawath Parnklang,Nutchaya Kaewraungrit,Sittisak Chaisotthe 제어로봇시스템학회 2008 제어로봇시스템학회 국제학술대회 논문집 Vol.2008 No.10

This article is a design of Charge pump circuit, which used CMOS transistor for generated high output DC voltage from the low 0.9v, 1.2v and 1.5v input DC voltage. Circuits are based on Dickson charge pump when forward bias to the substrate of MOSFET transistor structure of each state, this have an affect on the output to increase higher voltage. This body biased concept demonstrates by simulation program PSPICE using MOSIS model BSIM3V3. circuit comprises of biased voltage to substrate of NMOS transistor in Charge pump circuit. The circuit used MOSFET transistor N-type, P-type coupled in series with the input voltage to generated voltage is 0, 0.1, 0.2, 0.3, 0.4 and 0.5 V interconnected to the substrate of the NMOS. Two - overlapping clock signal driving the charge pump at 50 MHz. The circuit proved in the article have shown that can be adjust the value of output voltage, with from normal voltage will increase to voltage be equal to 20%, as the value of biased voltage to body equal to 0.5V.

TiO2−x –TiO2 Memristor Applications for Programmable Analog VLSI Circuits at 45 nm CMOS Technology Node

S. V. Abhay,Sanjay Vidhyadharan 한국전기전자재료학회 2021 Transactions on Electrical and Electronic Material Vol.22 No.4

Memristor-CMOS (MCM) technology combines CMOS processing with nano-scale memristors enabling a significant reduction in the silicon area as compared to CMOS-only counterparts. Moreover, the non-volatile memory characteristics of the memristor offers opportunity for new and innovative MCM hybrid VLSI circuits that can outperform conventional CMOS designs. MCM based hybrid, homogeneous re-configurable architectures have already gained immense popularity among digital VLSI designers. This paper explores application of TiO2−x –TiO2 charge trap memristor for programmable analog VLSI applications. The threshold adaptive memristor SPICE model has been used to evaluate the performance of the memristor in electronic design automation tool in conjunction with 45 nm CMOS devices. A digitally controlled MCM analog buffer, MCM binary phase shift keying modulator and a variable gain MCM differential amplifier has been presented in this paper. The MCM analog buffer has 81% greater gain-bandwidth product than the corresponding CMOS-only buffer and has an attenuation of −32 dB when the control signal is low. A MCM differential amplifier is proposed whose gain can be varied in both directions by shifting the operating point of the memristor through control signals, proving the advantages of using MCM technology for automatic gain control and other programmable analog VLSI applications. A MCM BPSK modulator circuit is also proposed which occupies 37.2% lesser silicon area than the conventional CMOS-only BPSK modulators, thus illustrating the utility of memristor in analog switching circuits.

전류구동 CMOS 다치 논리 회로설계 최적화연구

최재석,Choi, Jai-Sock 한국융합신호처리학회 2005 융합신호처리학회 논문지 (JISPS) Vol.6 No.3

전류모드 CMOS 회로기반 다치 논리 회로가 최근에 구현되고 있다. 본 논문에서는 4-치 Unary 다치 논리 함수를 전류모드 CMOS 논리 회로를 사용하여 합성하였다. 전류모드 CMOS(CMCL)회로의 덧셈은 각 전류 값들이 회로비용 없이 수행될 수 있고 또한 부의 논리 값은 전류흐름을 반대로 함으로써 쉽게 구현이 가능 하다. 이러한 CMCL 회로 설계과정은 논리적으로 조합된 기본 소자들을 사용하였다. 제안된 알고리듬을 적용한 결과 트랜지스터의 숫자를 고려하는 기존의 기법보다 더욱 적은 비용으로 구현할 수 있었다. 또한 비용-테이블 기법의 대안으로써 Unary 함수에 대해서 범용 UUPC(Universal Unary Programmable Circuit) 소자를 제안하였다. The implementation of Multiple-Valued Logic(MVL) based on Current-Mode CMOS Logic(CMCL) circuits has recently been achieved. In this paper, four-valued Unary Multiple-Valued logic functions are synthesized using current-mode CMOS logic circuits. We properly make use of the fact that the CMCL addition of logic values represented using discrete current values can be performed at no cost and that negative logic values are readily available via reversing the direction of current flow. A synthesis process for CMCL circuits is based upon a logically complete set of basic elements. Proposed algorithm results in less expensive realization than those achieved using existing techniques in terms of the number of transistors needed. As an alternative to the cost-table techniques Universal Unary Programmable Circuit (UUPC) for a unary function is also proposed.

Si PIN Radiation Sensor with CMOS Readout Circuit

권유미 ( Yu Mi Kwon ),강희성 ( Hee Sung Kang ),이정희 ( Jung Hee Lee ),이용수 ( Yong Soo Lee ) 한국센서학회 2014 센서학회지 Vol.23 No.2

Silicon PIN diode radiation sensors and CMOS readout circuits were designed and fabricated in this study. The PIN diodes were fabricated using a 380-μm-thick 4-inch n+ Si (111) wafer containing a 2-kΩ·cm n- thin epitaxial layer. CMOS readout circuits employed the driving and signal processes in a radiation sensor were mixed with digital logic and analog input circuits. The primary functions of readout circuits are amplification of sensor signals and the generation of the alarm signals when radiation events occur. The radiation sensors and CMOS readout circuits were fabricated in the Institute of Semiconductor Fusion Technology (ISFT) semiconductor fabrication facilities located in Kyungpook National University. The performance of the readout circuit combined with the Si PIN diode sensor was demonstrated.

커패시터 멀티플라이어를 갖는 CCM/DCM 이중모드 DC-DC 벅 컨버터의 설계

최진웅(Jin-Woong Choi),송한정(Han-Jung Song) 한국산학기술학회 2016 한국산학기술학회논문지 Vol.17 No.9

본 논문에서는 휴대 전자기기의 내부 전원단을 위한, CCM/DCM 기능의 이중모드 감압형 DC-DC 벅 컨버터를 제안한다. 제안하는 변환기는 1 MHz의 주파수에서 동작하며, 파워단과 제어블럭으로 이루어진다. 파워단은 Power MOS 트랜지스터, 인덕터, 커패시터, 제어 루프용 피드백 저항으로 구성된다. 제어부는 펄스폭 변조기 (PWM), 오차증폭기, 램프 파 발생기, 오실레이터 등으로 이루진다. 또한 본 논문에서 보상단의 큰 외부 커패시터는, 집적회로의 면적축소를 위하여 CMOS 회로로 구성되는 멀티플라이어 등가 커패시터로 대체하였다. 또한,. 본 논문에서, 보상단의 외부 커패시터는 집적회로의 면적을 줄이기 위하여 곱셈기 기반 CMOS 등가회로로 대체하였다. 또한 제안하는 회로는 칩을 보호하기 위하여 출력 과전압, 입력부족 차단 보호회로 및 과열 차단 보호회로를 내장하였다. 제안하는 회로는 0.18 ㎛ CMOS 공정을 사용하여, 케이던스의 스펙트라 회로설계 프로그램을 이용하여 설계 및 검증을 하였다. SPICE 모의 실험 결과, 설계된 이중모드 DC-DC 벅 변환기는 94.8 %의 피크효율, 3.29 mV의 리플전압, 2.7 ~ 3.3 V의 전압 조건에서 1.8 V의 출력전압을 보였다. This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 ㎒ consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a 0.18 ㎛ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

A Low-power CMOS Image Sensor Based on Variable Frame Rate Operation

Byoung-Soo Choi,Eunsu Shin,Myunghan Bae,Sang-Hwan Kim,Jimin Lee,Sang-Ho Seo,Jang-Kyoo Shin 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.6

Various circuits and devices are integrated on the CMOS image sensor (CIS) chip. Sources of power consumption in the CIS include source followers of the pixel array, bias circuits, driving circuits, a noise canceller, and readout circuits. In this paper, a low-power complementary metal oxide semiconductor (CMOS) image sensor based on variable frame rate operation is proposed. Power consumption of bias circuits and source followers of the pixel array is reduced by the variable frame rate operation in the proposed CIS. In most cases, the constant bias current continuously flows through the bias circuits and source followers even if the frame rate is changed. However, results indicate that using the variable frame rate operation reduces the constant bias current of the proposed CIS. Results also indicate that the power consumption is reduced by lowering the frame rate without significant image degradation.