The Characterizing Analysis of a Buried-Channel MOSFET based on the 3-D Numerical Simulation

Kim, Man-Ho,Kim, Jong-Soo The Korean Institute of Electrical Engineers 2007 Journal of Electrical Engineering & Technology Vol.2 No.2

A depletion-mode MOSFET has been analyzed to evaluate its electrical behavior using a novel 3-D numerical simulation package. The characterizing analysis of the BC MOSFET was performed through short-channel narrow-channel and small-geometry effects that are investigated, in detail, in terms of the threshold voltage. The DIBL effect becomes significant for a short-channel device with a channel length of $<\;3({\mu}m)$. For narrow-channel devices the variation of the threshold voltage was sharp for $<4({\mu}m)$ due to the strong narrow-channel effect. In the case of small-geometry devices, the shift of the threshold voltage was less sensitive due to the combination of the DIBL and substrate bias effects, as compared with that observed from the short-channel and narrow-channel devices. The characterizing analysis of the narrow-channel and small-geometry devices, especially with channel width of $<\;4({\mu}m)$ and channel area of $<\;4{\times}4({\mu}m^2)$ respectively, can be accurately performed only from a 3-D numerical simulation due to their sharp variations in threshold voltages.

The Characterizing Analysis of a Buried-Channel MOSFET based on the 3-D Numerical Simulation

Man-Ho Kim,Jongsoo Kim 대한전기학회 2007 Journal of Electrical Engineering & Technology Vol.2 No.2

A depletion-mode MOSFET has been analyzed to evaluate its electrical behavior using a novel 3-D numerical simulation package. The characterizing analysis of the BC MOSFET was performed through short-channel narrow-channel and small-geometry effects that are investigated, in detail, in terms of the threshold voltage. The DIBL effect becomes significant for a short-channel device with a channel length of < 3(㎛). For narrow-channel devices the variation of the threshold voltage was sharp for < 4(㎛) due to the strong narrow-channel effect. In the case of small-geometry devices, the shift of the threshold voltage was less sensitive due to the combination of the DIBL and substrate bias effects, as compared with that observed from the short-channel and narrow-channel devices. The characterizing analysis of the narrow-channel and small-geometry devices, especially with channel width of < 4(㎛) and channel area of < 4×4(㎛²) respectively, can be accurately performed only from a 3-D numerical simulation due to their sharp variations in threshold voltages.

Analysis of the Short-Channel Eect in 50 nm InAlAs/InGaAs Metamorphic High Electron Mobility Transistors

김삼동,이진구,임병옥,오정훈,이재서 한국물리학회 2008 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.53 No.6

We fabricate 50-nm InAlAs/InGaAs metamorphic high electron mobility transistors and investigate the short-channel effect by using a numerical analysis based on the hydrodynamic model. Our numerical approach is validated by comparing the computed values with the I-V characteristics measured from the fabricated devices at various bias conditions. From the analysis, we propose two different causes for the short-channel effect, depending on the gate bias condition. At small gate voltages of 0 ∽ -0.3 V, overflow of hot-electrons from the channel toward the buffer layers contribute to the non-zero output conductance at high Vds and the amount of this current component is quite significant and ∽1/6 the peak current density in the channel at a drain voltage of 1.6 V. At a higher gate voltage of -0.6 V, drain-induced barrier lowering plays a role in the significant increase of the output conductance above a drain voltage of 0.5 V. We fabricate 50-nm InAlAs/InGaAs metamorphic high electron mobility transistors and investigate the short-channel effect by using a numerical analysis based on the hydrodynamic model. Our numerical approach is validated by comparing the computed values with the I-V characteristics measured from the fabricated devices at various bias conditions. From the analysis, we propose two different causes for the short-channel effect, depending on the gate bias condition. At small gate voltages of 0 ∽ -0.3 V, overflow of hot-electrons from the channel toward the buffer layers contribute to the non-zero output conductance at high Vds and the amount of this current component is quite significant and ∽1/6 the peak current density in the channel at a drain voltage of 1.6 V. At a higher gate voltage of -0.6 V, drain-induced barrier lowering plays a role in the significant increase of the output conductance above a drain voltage of 0.5 V.

폴리 게이트의 양자효과에 의한 Double-Gate MOSFET의 특성 변화 연구

박지선,이승준,신형순 대한전자공학회 2004 電子工學會論文誌-SD (Semiconductor and devices) Vol.41 No.8

Density-gradient 방법을 이용하여 게이트의 양자효과가 double-gate MOSFET의 단채널 효과에 미치는 영향을 2차원으로 분석하였다. 게이트와 sidewall 산화막 경계면에서 발생하는 2차원 양자공핍 현상에 의하여 게이트 코너에 큰 전하 다이폴이 형성되며 subthreshold 영역에서 다이폴의 크기가 증가하고 classical 결과에 비하여 전자 농도와 전압 분포가 매우 다름을 알 수 있었다. Evanescent-nude분석을 통하여 게이트의 양자효과가 소자의 단채널 효과를 증가시키며 이는 기판에서의 양자효과에 의한 영향보다 크다는 것을 확인하였다. 양자효과에 의하여 게이트 코너에 형성되는 전하 다이폴이 단채널 효과를 증가시키는 원인임을 밝혔다. Quantum effects in the poly-gate are analyzed in two dimensions using the density-gradient method, and their impact on the short-channel effect of double-gate MOSFETs is investigated. The 2-D effects of quantum mechanical depletion at the gate to sidewall oxide is identified as the cause of large charge-dipole formation at the corner of the gate. The bias dependence of the charge dipole shows that the magnitude of the dipole peak-value increases in the subthreshold region and there is a large difference in carrier and potential distribution compared to the classical solution. Using evanescent-nude analysis, it is found that the quantum effect in the poly-gate substantially increases the short-channel effect and it is more significant than the quantum effect in the Si film. The penetration of potential contours into the poly-gate due to the dipole formation at the drain side of the gate corner is identified as the reason for the substantial increase in short-channel effects.

Influence of hetero-gate dielectrics on short-channel effects in scaled tunnel field-effect transistors

Nguyen Dang Chien,Luu The Vinh,Huynh Thi Hong Tham,Chun-Hsing Shih 한국물리학회 2020 Current Applied Physics Vol.20 No.12

In this study, we examined the influence of using hetero-gate dielectrics (HGDs) on the short-channel effects (SCEs) in scaled tunnel field-effect transistors (TFETs). For bulk TFETs, the short-channel performance is not influenced by the HGD engineering because the SCEs are caused by the tunneling at the region with negligible gate control. However, the use of the HGD increases the SCEs in double-gate TFETs because the HGD reduces the gate control on the channel. When the HGD optimized in term of on-current is used, the channel of HGD-TFETs is about 10-nm longer than that of uniform-gate dielectric TFETs to obtain similar SCEs. The SCEs in HGD-TFETs can be improved by locating the drain-side heterojunction toward the drain and/or increasing the ratio of lowand high-k equivalent oxide thicknesses. Due to the trend of scaling transistors, an appropriate design of HGD to minimize the SCEs in scaled HGD-TFETs is also crucial.

Control of Short-Channel Effects in Nano DG MOSFET Using Gaussian-Channel Doping Profile

Morteza Charmi 한국전기전자재료학회 2016 Transactions on Electrical and Electronic Material Vol.17 No.5

This article investigates the use of the Gaussian-channel doping profile for the control of the short-channel effectsin the double-gate MOSFET whereby a two-dimensional (2D) quantum simulation was used. The simulations werecompleted through a self-consistent solving of the 2D Poisson equation and the Schrodinger equation within thenon-equilibrium Green’s function (NEGF) formalism. The impacts of the p-type-channel Gaussian-doping profileparameters such as the peak doping concentration and the straggle parameter were studied in terms of the draincurrent, on-current, off-current, sub-threshold swing (SS), and drain-induced barrier lowering (DIBL). The simulationresults show that the short-channel effects were improved in correspondence with incremental changes of the straggleparameter and the peak doping concentration.

Control of Short-Channel Effects in Nano DG MOSFET Using Gaussian-Channel Doping Profile

Charmi, Morteza The Korean Institute of Electrical and Electronic 2016 Transactions on Electrical and Electronic Material Vol.17 No.5

This article investigates the use of the Gaussian-channel doping profile for the control of the short-channel effects in the double-gate MOSFET whereby a two-dimensional (2D) quantum simulation was used. The simulations were completed through a self-consistent solving of the 2D Poisson equation and the Schrodinger equation within the non-equilibrium Green’s function (NEGF) formalism. The impacts of the p-type-channel Gaussian-doping profile parameters such as the peak doping concentration and the straggle parameter were studied in terms of the drain current, on-current, off-current, sub-threshold swing (SS), and drain-induced barrier lowering (DIBL). The simulation results show that the short-channel effects were improved in correspondence with incremental changes of the straggle parameter and the peak doping concentration.

진공 게이트 스페이서를 지니는 Bulk FinFET의 단채널효과 억제를 위한 소자구조 최적화 연구

연지영 ( Ji-yeong Yeon ),이광선 ( Khwang-sun Lee ),윤성수 ( Sung-su Yoon ),연주원 ( Ju-won Yeon ),배학열 ( Hagyoul Bae ),박준영 ( Jun-young Park ) 한국전기전자재료학회 2022 전기전자재료학회논문지 Vol.35 No.6

Semiconductor devices have evolved from 2D planar FETs to 3D bulk FinFETs, with aggressive device scaling. Bulk FinFETs make it possible to suppress short-channel effects. In addition, the use of low-k dielectric materials as a vacuum gate spacer have been suggested to improve the AC characteristics of the bulk FinFET. However, although the vacuum gate spacer is effective, correlation between the vacuum gate spacer and the short-channel-effects have not yet been compared or discussed. Using a 3D TCAD simulator, this paper demonstrates how to optimize bulk FinFETs including a vacuum gate spacer and to suppress short-channel effects.

SiGe을 소스 접합 물질로 사용하는 터널링 전계효과 트랜지스터의 성능 및 짧은 채널 효과 분석

정영훈(Yunghun Jung),조용범(Yongbeom Cho),강인만(In Man Kang),조성재(Seongjae Cho) 대한전자공학회 2017 전자공학회논문지 Vol.54 No.12

본 논문에서는 Si 기반의 터널링 전계효과 트랜지스터(tunneling field-effect transistor, TFET)의 낮은 전류 구동 능력을 향상시키기 위해 소스 접합에 Si1-xGex을 적용한 이종접합 기반의 Si1-xGex 터널링 전계효과 트랜지스터의 성능을 분석하고 주어진 소자에서 나타날 수 있는 짧은 채널 효과(short-channel sffects)의 양상을 살펴본다. Ge 함량(x)의 변화에 따른 소스 접합물질의 에너지 밴드갭 변화와 에너지 자리 밀도(density of states)의 변화의 결과로 나타나는 켜진 상태 전류의 변화에 초점을 두어 분석을 수행하였다. 더불어, 향후 10 nm 이하 기술 노드(technology node)에서의 소자 적용 가능성을 확인함과 동시에 짧은 채널에서 나타나는 비이상적인 효과들을 살펴보기 위해 채널 길이(Lch)를 28 nm, 14 nm, 10 nm, 7 nm로 변화시키면서 시뮬레이션을 수행하였다. Lch이 짧아질수록 소스와 드레인 간의 전기장의 겹침으로 채널의 일부 영역에서 인해 펀치스루 (punch-through) 현상이 발행하여 TFET의 스위칭 특성이 열화되는 것을 확인하였다. 나아가, Lch의 변화에 따른 고속 동작특성 변화를 확인하기 위해 fT 및 fmax를 추출하였으며 Lch가 짧아질수록 단조증가하는 경향을 확인하였다. In this paper, we present the device performances of Si1-xGex heterojunction tunneling field-effect transistor (TFET) having Si1-xGex source junction specifically designed for improving the rather low on-state current (Ion) of Si TFET and have a look into the short-channel effects (SCEs) which might take place in the device. The analyses are performed with a focus on the relation between Ge fraction (x) and Ion under the influences of changes in energy bandgap and density of states (DOS) in the Si1-xGex source junction as a function of x. Also, in order to evaluate the possibility of application of the Si1-xGex TFET to the upcoming sub-10-nm technology nodes and the non-ideal effects arising from the extremely short-channel TFETs simultaneously, the device simulations were performed with scaling the channel length: 28 nm, 14 nm, 10 nm, and 7 nm. It is confirmed that the switching characteristics of Si1-xGex TFET are degraded as Lch is shrunken, due to the electric field overlap between source and drain in a part of channel leading to punch-through. Furthermore, in order to investigate the high-speed operation characteristics, fT and fmax were extracted from the devices with different Lch’s and it was verified that those parameters maintained the tendency of increase as Lch gets shorter.

A Compact Model of Gate-Voltage-Dependent Quantum Effects in Short-Channel Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

Jihyun Kim,Wookyung Sun,Seunghye Park,Hyein Lim,Hyungsoon Shin 대한전자공학회 2011 Journal of semiconductor technology and science Vol.11 No.4

In this paper, we present a compact model of gate-voltage-dependent quantum effects in shortchannel surrounding-gate (SG) metal-oxide-semiconductor field-effect transistors (MOSFETs). We based the model on a two-dimensional (2-D) analytical solution of Poisson’"s equation using cylindrical coordinates. We used the model to investigate the electrostatic potential and current sensitivities of various gate lengths (Lg) and radii (R). Schrodinger’"s equation was solved analytically for a one-dimensional (1-D) quantum well to include quantum effects in the model. The model takes into account quantum effects in the inversion region of the SG MOSFET using a triangular well. We show that the new model is in excellent agreement with the device simulation results in all regions of operation.