Non-Overlapped Single/Double Gate SOI/GOI MOSFET for Enhanced Short Channel Immunity

Sharma, Sudhansh,Kumar, Pawan The Institute of Electronics and Information Engin 2009 Journal of semiconductor technology and science Vol.9 No.3

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

Non-Overlapped Single/Double Gate SOI/GOI MOSFET for Enhanced Short Channel Immunity

Sudhansh Sharma,Pawan Kumar 대한전자공학회 2009 Journal of semiconductor technology and science Vol.9 No.3

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon?on?Insulator (SOI) and Germanium?on?Insulator (GOI) MOSFETs. A design methodology, by evaluating the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non?overlapped gate?source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

Leakage current reduction in nanoscale fully-depleted SOI MOSFETs with modified current mechanism

Ali A. Orouji,Morteza Rahimian 한국물리학회 2012 Current Applied Physics Vol.12 No.5

For the first time, we have presented a novel nanoscale fully depleted silicon-on-insulator metal-oxidesemiconductor field-effect transistor (SOI-MOSFET) with modified current mechanism for leakage current reduction. The key idea in this work is to suppress the leakage current by injected carriers decrement into the channel from the source in weak inversion regime while we have created a built-in electric field in the channel for improving the on current of device. Therefore, we have introduced a trapezoidal doping that distributed vertically in the channel and called the proposed structure as vertical trapezoid doping fully depleted silicon-on-insulator MOSFET (VTD-SOI). Using two-dimensional two-carrier simulation we demonstrate that the VTD-SOI decreases the leakage current in comparison with conventional uniform doping fully depleted silicon-on-insulator MOSFET (C-SOI). Also, our results show short channel effects (SCEs) such as drain induced barrier lowering (DIBL) and threshold voltage roll-off improvement in the proposed structure. Therefore, the VTD-SOI structure shows excellent performance for scaled transistors in comparison with the C-SOI and can be a good candidate for CMOS low power circuits.

Commercial Silicon-on-Insulator (SOI) Wafers as a Versatile Substrate for Laser Desorption/Ionization Mass Spectrometry

Kim, Shin Hye,Kim, Jeongkwon,Moon, Dae Won,Han, Sang Yun Springer-Verlag 2013 Journal of the American Society for Mass Spectrome Vol.24 No.1

<P>We report here that a commercial silicon-on-insulator (SOI) wafer offers an opportunity for laser desorption/ionization (LDI) of peptide molecules, which occurs directly from its flat surface without requiring special surface preparation. The LDI-on-SOI exhibits intact ionization of peptides with a good detection limit of lower than 20 fmol, of which the mass range is demonstrated up to insulin with citric acid additives. The LDI process most likely arises from laser-induced surface heating promoted by two-dimensional thermal confinement in the thin Si surface layer of the SOI wafer. As a consequence of the thermal process, the LDI-on-SOI method is also capable of creating post-source decay (PSD) of the resulting peptide LDI ions, which is suitable for peptide sequencing using conventional TOF/TOF mass spectrometry.</P> [FIG OMISSION]</BR>

Impact of Back Gate Bias on Analog Performance of Dopingless Transistor

Rakesh Kumar,Meena Panchore 한국전기전자재료학회 2023 Transactions on Electrical and Electronic Material Vol.24 No.1

In this brief, the impact of back gate bias (Vgb) , on analog performance of silicon on insulator dopingless transistor (SOIDLT) is investigated. It is observed that SOI-DLTs are more immune to Vgb in contrast to its conventional counterpart SOI junctionless transistor (SOI-JLT). When Vgb is increased from -1.5 V to 1.5 V, the variation in transconductance (gm) and intrinsic gain ( gmrO ) of SOI-JLT is 1.3 and 21.4 times higher than SOI-DLT. The insignifi cant variation is observed in gm and gmrO of SOI-DLT against V gb than SOI-JLT due to the use of lightly doped channel. Further, the device reliability of SOI-DLT against impact ionization is evaluated by measuring the electron concentration and electric field near the drain side. We have found that the SOI-DLT is less sensitive to impact ionization in comparison to conventional SOI-JLT. Hence, the simulation results shown in this paper offer an opportunity for future analog integrated circuits designing with SOI-DLT structure under the influence of Vgb .

Wet Etching Technique for Reliable Optical Measurement of Defect Density in Thin Silicon-on-Insulator

Kang, Hee-Sung,Ahn, Chang-Geun,Lee, Seok-Ha,Kim, Kwang-Il,Bae, Young-Ho,Kwon, Young-Kyu,Kang, Bongkoo 위덕대학교 부설 전자기술연구소 1997 전자기술연구소 논문집 : 위덕대 Vol.1 No.1

An optical measurement is desired for reliable wafer-scale measurement of crystalline defects in a silicon-on-insulator (SOI) layer. Using a oxygen-implanted SOI layer, a chemical wet etching technique based on the three step etch pit transfer method has been investigated to form etch pits of appropriate size for reliable wafer-scale optical measurement of the defects in the SOI layer. The etch steps consist of a SOI etching with a dilute Wright etching solution, a buried oxide (BOX) etching with a hydrofluoric acid solution, and a substrate silicon etching with the standard Wright etching solution. To find an optimum condition for optical measurement of defect density, etching conditions are varied to enlarge the etch pits to an optimum size. The densities of magnified etch pits are measured with an automatic optical image analyzer, and the results agree well with the defect density observed by cross-sectional transmission electron microscope (TEM).

SOI 응용을 위한 반도체-원자 초격자 다이오드의 광전자 특성

서용진 한국마이크로전자및패키징학회 2003 마이크로전자 및 패키징학회지 Vol.10 No.3

증착온도와 어닐링 조건에 따른 반도체-원자 초격자 구조의 광전자특성이 연구되었다. 나노결정의 Si-O 초격자 구조는 MBE 시스템에 의해 형성되었다. 다층의 Si-O 초격자 다이오드는 매우 안정한 포토루미네슨스 특성과 높은 브레이크다운 전압을 갖는 양호한 절연 특성을 나타내었다. 이러한 결과는 미래의 초고속 및 저전력 CMOS 소자에서 SOI 구조의 대체 방안으로 사용될 수 있을 뿐만 아니라, 실리콘계 광전자 소자 및 양자 전자 소자에도 응용될 수 있을 것이다. The optoelectronic characteristics of semiconducto-atomic superlattice as a function of deposition temperature and annealing conditions have been studied. The nanocrystalline silicon/adsorbed oxygen superlattice formed by molecular beam epitaxy(MBE) system. As an experimental result, the superlattice with multilayer Si-O structure showed a stable photoluminescence(PL) and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronics and quantum devices as well as for the replacement of silicon-on-insulator (SOI) in ultra-high speed and lower power CMOS devices in the future, and it can be directly integrated with silicon ULSI processing.

Signal Enhancement of Silicon Nanowire-Based Biosensor for Detection of Matrix Metalloproteinase-2 Using DNA-Au Nanoparticle Complexes

Choi, Jin-Ha,Kim, Han,Choi, Jae-Hak,Choi, Jeong-Woo,Oh, Byung-Keun American Chemical Society 2013 ACS APPLIED MATERIALS & INTERFACES Vol.5 No.22

<P>Silicon nanowires have been used in the development of ultrasensitive biosensors or chemical sensors, which is originated in its high surface-to-volume ratio and function as field-effect transistor (FET). In this study, we developed an ultrasensitive DNA-gold (Au) nanoparticle complex-modified silicon nanowire field effect transistor (SiNW-FET) biosensor to detect matrix metalloproteinase-2 (MMP-2), which has been of particular interest as protein biomarker because of its relation to several important human diseases, through an enzymatic cleavage reaction of a specific peptide sequence (IPVSLRSG). SiNW patterns with a width of 100 nm and height of 100 nm were fabricated on a p-type silicon-on-insulator (SOI) wafer by electron-beam lithography. Next, negatively charged DNA-Au nanoparticle complexes coupled with the specific peptide (KKGGGGGG-IPVSLRSG-EEEEEE) were applied on the SiNWs to create a more sensitive system, which was then bound to aldehyde-functionalized SiNW. The enhanced negatively charged nanoparticle complexes by attached DNA were used to enhance the conductance change of the <I>p</I>-SiNW by MMP-2 cleavage reaction of the specific peptide. MMP-2 was successfully measured within a range of 100 fM to 10 nM, and the conductance signal of the p-type SiNW by the MMP-2 cleavage reaction was enhanced over 10-fold by using the DNA-Au nanoparticle complexes compared with using SiNW-attached negative single peptide sequences.</P><P><B>Graphic Abstract</B> <IMG SRC='http://pubs.acs.org/appl/literatum/publisher/achs/journals/content/aamick/2013/aamick.2013.5.issue-22/am403816x/production/images/medium/am-2013-03816x_0007.gif'></P>

A Novel High Performance SOI LDMOS with Buried Stepped Gate Field Plate

Hongchao Hu,Hongli Dai,Luoxin Wang,Haitao Lyu,Yuming Xue,Tu Qian 한국전기전자재료학회 2023 Transactions on Electrical and Electronic Material Vol.24 No.6

With the continuous development of science and technology, the power semiconductor devices are becoming more and more extensive. A novel silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor (LDMOS) has been proposed in this paper. The new device is mainly characterized by introducing a stepped gate field plate in the low-K dielectric buried layer (SGFP-LK). On the one hand, the stepped gate field plate introduces extra lateral electric field peaks, which makes the distribution of potential lines more uniform and improves the breakdown voltage (BV). Moreover, the stepped gate fi eld plate decreases the specific on-resistance ( R on,sp ) by a promoted depletion. On the other hand, different from the traditional buried oxygen layer, the low-K dielectric layer strengthens the vertical electric field and signifi cantly increases BV. Ultimately, compared with the conventional device (C-SOI LDMOS), the BV of the SGFP-LK LDMOS is dramatically enhanced by 107% and the R on,sp is reduced by 24.8%. Furthermore, the figure of merit is enhanced by 472%. In addition, the maximum lattice temperature of the SGFP-LK LDMOS is dropped by 23.1 K, which relieves self-heating effects to some extent.

An L-band Stacked SOI CMOS Amplifier

Kim, Young-Gi,Hwang, Jae-Yeon Institute of Korean Electrical and Electronics Eng 2016 전기전자학회논문지 Vol.20 No.3

This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm. This paper presents a two stage L-band power amplifier realized with a $0.32{\mu}m$ Silicon-On-Insulator (SOI) CMOS technology. To overcome a low breakdown voltage limit of MOSFET, stacked-FET structures are employed, where three transistors in the first stage amplifier and four transistors in the second stage amplifier are connected in series so that their output voltage swings are added in phase. The stacked-FET structures enable the proposed amplifier to achieve a 21.5 dB small-signal gain and 15.7 dBm output 1-dB compression power at 1.9 GHz with a 122 mA DC current from a 4 V supply. The amplifier delivers a 19.7 dBm saturated output power with a 16 % maximum Power Added Efficiency (PAE). A bond wire fine tuning technology enables the amplifier a 23.67 dBm saturated output power with a 20.4 % maximum PAE. The die area is $1.9mm{\times}0.6mm$.