Jungian Character Network in Growing Other Character Archetypes in Films

Youngsue Han 한국콘텐츠학회(IJOC) 2019 International Journal of Contents Vol.15 No.2

This research demonstrates a clear visual outline of character influence-relations in creating Jungian character archetypes in films using R computational technology. It contributes to the integration of Jungian analytical psychology into film studies by revealing character network relations in film. This paper handles character archetypes and their influence on developing other character archetypes in films in regards to network analysis drawn from Lynn Schmidt’s analysis of 45 master characters in films. Additionally, this paper conducts a character network analysis visualization experiment using R open-source software to create an easily reproducible tutorial for scholars in humanities. This research is a pioneering work that could trigger the academic communities in humanities to actively adopt data science in their research and education.

Developing Electronic Maps on First-run and Doublefeature Cinemas in Seoul from 1976 to 1995

Youngsue Han,Hyunjung Roh,Whelan Thomas,Jisun Park,Jieun Kim 한국콘텐츠학회(IJOC) 2023 International Journal of Contents Vol.19 No.4

This paper evaluated the geographical distribution, chronological and economic patterns of the commercial cinema industry in Seoul, Korea dichotomized by the two main types of cinemas that have been prevalent in the recent Korean history, the first-run cinemas and the double-feature cinemas. This analysis involved computational technologies including the R statistical programing language and the interactive map library known as Leaflet for R in order to scrutinize the aforementioned patterns. Historically the cinema industry has been under the tight control of authoritarian military dictatorships that have run Korea in past decades, and the measures they took to control the cinema industry leading to unexpected ramifications. One of them is the decrease in the quality of domestic films, as competition with international films was reduced, and another is the massive increase in the domestic production of low-quality sex-exploitation B-tier films. The double feature cinemas played a big role in the distribution of the low- quality films. Our electronic maps will clearly represent the hierarchy and differentiation of these cinemas in the cinematic landscape of Seoul.

Optimal Design of the Task-oriented Wearable Robot for the Upper Extremity

YoungSu Lee,SeungHoon Lee,SeungNam Yu,JaeHo Jang,ChangSoo Han,JungSoo Han 제어로봇시스템학회 2009 제어로봇시스템학회 국제학술대회 논문집 Vol.2009 No.8

This study presents several measures aimed at mathematically quantifying characteristics associated withhuman performance and wearable robot platform; there will be trials for improving the kinematic performance of the proposed wearable robot system through the optimization methodology. Within constrained conditions, optimal link lengths will be defined for its objectives and purposes. In particular, parameters from these studies and experiments, isone way of improving its performance of function-orient human robot corporative system; they are used for quantifying the feeling of putting on platform and flexibility, too.

A 32TFLOPS AI Processor with 1GHz General NN Accelerator

Youngsu Kwon,Yongcheol Peter Cho,Jeongmin Yang,Jaehoon Chung,Kyoung-Seon Shin,Jinho Han,Chan Kim,Chun-Gi Lyuh,Hyun-Mi Kim,Insan Jeon,Min-Seok Choi 대한전자공학회 2019 대한전자공학회 학술대회 Vol.2019 No.6

40-TFLOPS artificial intelligence processor with function-safe programmable many-cores for ISO26262 ASIL-D

Han, Jinho,Choi, Minseok,Kwon, Youngsu Electronics and Telecommunications Research Instit 2020 ETRI Journal Vol.42 No.4

The proposed AI processor architecture has high throughput for accelerating the neural network and reduces the external memory bandwidth required for processing the neural network. For achieving high throughput, the proposed super thread core (STC) includes 128 × 128 nano cores operating at the clock frequency of 1.2 GHz. The function-safe architecture is proposed for a fault-tolerance system such as an electronics system for autonomous cars. The general-purpose processor (GPP) core is integrated with STC for controlling the STC and processing the AI algorithm. It has a self-recovering cache and dynamic lockstep function. The function-safe design has proved the fault performance has ASIL D of ISO26262 standard fault tolerance levels. Therefore, the entire AI processor is fabricated via the 28-nm CMOS process as a prototype chip. Its peak computing performance is 40 TFLOPS at 1.2 GHz with the supply voltage of 1.1 V. The measured energy efficiency is 1.3 TOPS/W. A GPP for control with a function-safe design can have ISO26262 ASIL-D with the single-point fault-tolerance rate of 99.64%.

80 µW/MHz, 850 MHz Fault Tolerant Processor with Fault Monitor Systems

Han, Jinho,Kwon, Youngsu,Shin, Kyeongsun,Yoo, Hoi-Jun The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.5

The processor is becoming increasingly susceptible to transient faults with fluctuating voltage, widening operating temperature, and increasing clock frequency. Especially, processor, operating near threshold voltage for a low power, can expose to transient faults with the thin margin of process, voltage, and temperature. This paper presents a fault tolerant processor having on-chip fault monitor systems for processor core and cache, which detects faults and corrects faults, and a fault injector which injects faults for testing. The fault tolerant feature is analyzed by a fault injection and quantitative analysis complying with ISO26262 standard. As a result, the proposed work achieves $80{\mu}W/MHz$ energy efficiency, 850 MHz maximum frequency, 72% fault trap reduction, and 99.23% single point fault failure rate complying with ISO26262.

80 μW/MHz, 850 MHz Fault Tolerant Processor with Fault Monitor Systems

Jinho Han,Youngsu Kwon,Kyeongsun Shin,Hoi-Jun Yoo 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.5

The processor is becoming increasingly susceptible to transient faults with fluctuating voltage, widening operating temperature, and increasing clock frequency. Especially, processor, operating near threshold voltage for a low power, can expose to transient faults with the thin margin of process, voltage, and temperature. This paper presents a fault tolerant processor having on-chip fault monitor systems for processor core and cache, which detects faults and corrects faults, and a fault injector which injects faults for testing. The fault tolerant feature is analyzed by a fault injection and quantitative analysis complying with ISO26262 standard. As a result, the proposed work achieves 80 μW/MHz energy efficiency, 850 MHz maximum frequency, 72% fault trap reduction, and 99.23% single point fault failure rate complying with ISO26262.

80μW/MHz 0.68V Ultra Low-Power Variation-Tolerant Superscalar Dual-Core Application Processor

Kwon, Youngsu,Lee, Jae-Jin,Shin, Kyoung-Seon,Han, Jin-Ho,Byun, Kyung-Jin,Eum, Nak-Woong The Institute of Electronics and Information Engin 2015 IEIE Transactions on Smart Processing & Computing Vol.4 No.2

Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of $80{\mu}W/MHz$. The operating frequency of the core reaches 850MHz at 1.2V.

선박에서 증강현실 위치 정합 활용을 위한 기계학습 기반의 마커 복원 방법 연구

김영수(Youngsu Kim),이경호(Kyungho Lee),한영수(Young-Soo Han),여현빈(Hyunbin-Yeo) (사)한국CDE학회 2022 한국CDE학회 논문집 Vol.27 No.4

The interior of the ship is very complex and the equipment is equipped with pipes, valves, supports, etc. In order to utilize augmented reality in such an environment, it is more appropriate to use markers rather than markerless, which creates a model based on the characteristics of the target equipment. However, it is difficult to apply the marker because a lot of corrosion or damage to the marker may occur in the ship. Therefore, in this study, when a marker is damaged, it is intended to restore the marker using GAN among machine learning techniques. At this time, the model was built using the Pix2Pix, Cycle GAN, and Disco GAN algorithms widely used for images among GAN algorithms. Finally, an efficient marker restoration algorithm was verified by qualitatively and quantitatively comparing the model results.

알데바란 프로세서를 이용한 오류 감내 기능이 있는 자동차용 프로세서

한진호(Jinho Han),권영수(Youngsu Kwon) 대한전자공학회 2016 대한전자공학회 학술대회 Vol.2016 No.6

Advanced Driver Assistant System using vision processing is being equipped in automotive industries. Automotive processor , having the higher performance than one for engine and body control of vehicle is needed for the vision processing. So, We developed automotive processor with a fault tolerant feature and high performance for Automotive Vision Processor. First, We developed Aldebaran processor having 13 stage pipelines, dual-issue superscalar architecture, and caches. Second, We developed the fault tolerant feature in the cache and core of Aldebaran processor. We implemented the processor using FPGA and verified by running the Lane Departure Warning Algorithm.