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Kim, Jonghoon J.,Heegon Kim,Jung, Daniel H.,Sumin Choi,Jaemin Lim,Youngwoo Kim,Junyong Park,Hyesoo Kim,Dongho Ha,Bae, Michael,Joungho Kim IEEE 2017 IEEE transactions on electromagnetic compatibility Vol.59 No.4
<P>As the data rate of Low Power Double Data Rate 4 (LPDDR4) memory now exceeds 3.2 Gb/s, it is becoming more difficult to meet the target specifications. While testing has become of utmost importance, it is not viable to have a direct access to the signal pins in a package on package configuration due to the densely located array of solder balls; instead, a test interposer with an excellent electrical performance needs to be adopted to provide test access. In this paper, we first propose a novel test interposer scheme for testing LPDDR4 memory packages. For accurate testing without significant influence on the intrinsic signal path, the proposed test interposer is designed considering a number of signal integrity issues such as intersymbol interference, jitter, impedance matching, and crosstalk. Furthermore, by adopting silicone rubber sheet in place of soldering, the proposed test interposer enhances reusability of the packages with a fast setup time. Moreover, a reconstruction method is proposed that can reconstruct the voltage at application processor using the waveform captured on the test interposer, instead of probing at the ball gray array directly. Through a series of simulations and measurements, we experimentally verified the proposed test interposer. The proposed test interposer scheme can be widely adopted for testing of high-performance packages with its high accuracy and practicality.</P>
Kim, Jonghoon J.,Changhyun Cho,Bumhee Bae,Sukjin Kim,Sunkyu Kong,Heegon Kim,Jung, Daniel H.,Jiseong Kim,Joungho Kim IEEE 2014 IEEE transactions on components, packaging, and ma Vol.4 No.12
<P>A simultaneous switching current (SSC) drawn by an integrated circuit (IC) creates simultaneous switching noise on power nets, which in turn causes jitters in the I/O signals and reduces the maximum clock frequency. For a thorough analysis of high-speed ICs, there is a dire need to measure currents at specific power pins of the ICs. In this paper, a novel magnetically coupled embedded current probing structure is proposed for measuring the SSC on the chip level resulting from the logical activity of the I/O buffers. SSCs are found by capturing the magnetic flux induced by the SSC of interest, with the proposed embedded current probing structure using magnetic coupling, and then reconstructing the original current waveform using the transfer impedance profile. Through a series of measurements with test vehicles fabricated on the chip level, we experimentally verified the proposed probing structures in the time and frequency domains and proved that they can effectively measure the SSC. Finally, future directions for improvements are discussed at the end of this paper.</P>
Jonghoon Kim,Hongseok Kim,In-Myoung Kim,Young-Il Kim,Seungyoung Ahn,Jiseong Kim,Joungho Kim 한국전자파학회JEES 2011 Journal of Electromagnetic Engineering and Science Vol.11 No.3
In this paper, we implemented and analyzed a wireless power transfer (WPT) system with a CSPR topology. CSPR refers to constant current source, series resonance circuit topology of a transmitting coil, parallel resonance circuit topology of a receiving coil, and pure resistive loading. The transmitting coil is coupled by a magnetic field to the receiving coil without wire. Although the electromotive force (emf) is small (about 4.5V), the voltage on load resistor is 148V, because a parallel resonance scheme was adopted for the receiving coil. The implemented WPT system is designed to be able to transfer up to 1 ㎾ power and can operate a LED TV. Before the implementation, the EMF reduction mechanism based on the use of ferrite and a metal shield box was confirmed by an EM simulation and we found that the EMF can be suppressed dramatically by using this shield. The operating frequency of the implemented WPT system is 30.7㎑ and the air gap between two coils is 150㎜. The power transferred to the load resistor is 147W and the real power transfer efficiency is 66.4 %.
30 Gbps High-Speed Characterization and Channel Performance of Coaxial Through Silicon Via
Jung, Daniel H.,Heegon Kim,Sukjin Kim,Kim, Jonghoon J.,Bumhee Bae,Jonghoon Kim,Jong-Min Yook,Jun-Chul Kim,Joungho Kim THE INSTITUTE OF ELECTRICAL ENGINEERS 2014 IEEE Microwave and Wireless Components Letters Vol. No.
<P>Coaxial through silicon via (TSV) technique allows reduction of high frequency loss due to conductivity in silicon substrate and flexibility in impedance by controlling the ratio of shield to center radii. For the first time, we measured and analyzed the high-speed channel performance of coaxial TSV. This letter presents the measurement results of the fabricated test vehicle in S-parameter and eye-diagram. The eye-diagram measurement results prove that coaxial TSV is capable of supporting signal transmission up to bit rate of 30 Gbps. The equivalent circuit model is suggested and experimentally verified by S-parameter comparison. Furthermore, the superiority of coaxial TSV over conventional TSV is confirmed by comparison of S-parameter results from equivalent circuit model simulation.</P>
Kim Eun-Kyung,Fenyi Justice Otoo,Kim Jae-Hee,Kim Myung-Hee,Yean Seo-Eun,Park Kye-Wol,Oh Kyungwon,윤성하,Ishikawa-Takata Kazuko,Park Jonghoon,Kim Jung Hyun,Yoon Jin-Sook 한국영양학회 2022 Nutrition Research and Practice Vol.16 No.5
BACKGROUND/OBJECTIVES The doubly labeled water (DLW) method is the gold standard for estimating total energy expenditure (TEE) and is also useful for verifying the validities of dietary evaluation tools. In this study, we compared the accuracy of total energy intakes (TEI) estimated by the 24-h diet recall method with TEE obtained using the doubly labeled water method. SUBJECTS/METHODS This study involved 71 subjects aged 20–49 yrs. Over a 14-day period, three 24-h diet recalls per subject (2 weekdays and 1 weekend day) were used to estimate energy intakes, while TEE was measured using the DLW method. The paired t-test was used to determine the significance of differences between TEI and TEE results, and the accuracy of the 24-h recall method was determined by accuracy predictions percentage, root mean square error, and bias. RESULTS Average study subject age was 33.4 ± 8.6 yrs. The association between TEI and TEE was positive and significant (r = 0.463, P < 0.001), and the difference between TEI (2,084.3 ± 684.2 kcal/day) and TEE (2,401.7 ± 480.3 kcal/day) was also significant (P < 0.001). In all study subjects, mean TEI was 12.0% (307.5 ± 629.3 kcal/day) less than mean TEE, and 12.2% (349.4 ± 632.5 kcal/day) less in men and 11.8% (266.7 ± 632.5 kcal/day) less in women. Rates of TEI underprediction for all study subjects, men, and women, were 60.5%, 51.4%, and 66.7%, respectively. CONCLUSIONS This study shows that 24-h diet recall underreports energy intakes. More research is needed to corroborate our findings and evaluate the accuracy of 24-h recall with respect to additional demographics.
Through-Silicon Via Capacitance–Voltage Hysteresis Modeling for 2.5-D and 3-D IC
Kim, Dong-Hyun,Kim, Youngwoo,Cho, Jonghyun,Bae, Bumhee,Park, Junyong,Lee, Hyunsuk,Lim, Jaemin,Kim, Jonghoon J.,Piersanti, Stefano,de Paulis, Francesco,Orlandi, Antonio,Kim, Joungho IEEE 2017 IEEE transactions on components, packaging, and ma Vol.7 No.6
<P>We propose, for the first time, an explicit semiconductor physics-based through-silicon via (TSV) capacitance-voltage (CV) model. The effect of TSV CV hysteresis is demonstrated in the model, and the TSV capacitance is modeled with respect to dc bias voltage and the dimension of the TSV. The proposed model is verified by comparison to the measurement results. The effect of hysteresis in the model correlates well with the measurement results. This model can be utilized in a circuit level simulation to expand the possible application of the model to, but not limited to, hierarchical power distribution network impedance analysis, RC delay analysis, input-output power consumption analysis, and crosstalk and eye diagram simulation in any 3-D-IC systems using TSVs.</P>
Kim, Youngwoo,Cho, Jonghyun,Kim, Jonghoon J.,Cho, Kyungjun,Kim, Subin,Sitaraman, Srikrishna,Sundaram, Venky,Raj, Pulugurtha Markondeya,Tummala, Rao R.,Kim, Joungho [Institute of Electrical and Electronics Engineers 2017 IEEE transactions on electromagnetic compatibility Vol.59 No.3
<P>In this paper, we propose glass interposer electromagnetic bandgap (EBG) structure to efficiently suppress power/ground noise coupling. We designed, fabricated, measured, and analyzed a glass interposer EBG structure for the first time. Glass interposer EBG structure test vehicles were fabricated using a thin-glass substrate, low-loss polymer layers, and periodic metal patches with through glass vias (TGVs) in glass interposer power distribution network. Using the dispersion characteristics, we thoroughly analyzed and derived f(L) and f(U) of the glass interposer EBG structure. We experimentally verified that the proposed glass interposer EBG structure achieved power/ground noise suppression (below -40 dB) between f(L) of 5.8 GHz and f(U) of 9.6 GHz. Derived f(L) and f(U) based on dispersion analysis, full three-dimensional electromagnetic (3-D-EM) simulation and measurement achieved good correlation. In the glass interposer EBG structure, tapered structure of the TGV and thickness of the low-loss polymer used for metal-layers lamination affected the noise suppression bandgap significantly. The effectiveness of the proposed glass interposer EBG structure on suppression of the power/ground noise propagation and coupling to high-speed TGV channel was verified with 3-D-EM simulation. As a result, the proposed glass interposer EBG structure successfully and efficiently suppressed the power/ground noise propagation and improved eye-diagram of the high-speed TGV channel.</P>
지능형 서비스 로봇을 위한 온톨로지 기반의 동적 상황 관리 및 시-공간 추론
김종훈(Jonghoon Kim),이석준(Seokjun Lee),김동하(Dongha Kim),김인철(Incheol Kim) Korean Institute of Information Scientists and Eng 2016 정보과학회논문지 Vol.43 No.12
One of the most important capabilities for autonomous service robots working in living environments is to recognize and understand the correct context in dynamically changing environment. To generate high-level context knowledge for decision-making from multiple sensory data streams, many technical problems such as multi-modal sensory data fusion, uncertainty handling, symbolic knowledge grounding, time dependency, dynamics, and time-constrained spatio-temporal reasoning should be solved. Considering these problems, this paper proposes an effective dynamic context management and spatio-temporal reasoning method for intelligent service robots. In order to guarantee efficient context management and reasoning, our algorithm was designed to generate low-level context knowledge reactively for every input sensory or perception data, while postponing high-level context knowledge generation until it was demanded by the decision-making module. When high-level context knowledge is demanded, it is derived through backward spatio-temporal reasoning. In experiments with Turtlebot using Kinect visual sensor, the dynamic context management and spatio-temporal reasoning system based on the proposed method showed high performance.
Sukjin Kim,Jung, Daniel H.,Kim, Jonghoon J.,Bumhee Bae,Sunkyu Kong,Seungyoung Ahn,Jonghoon Kim,Joungho Kim IEEE 2015 IEEE transactions on components, packaging, and ma Vol.5 No.7
<P>As technology develops, the number of chips increases while the thickness of mobile products continuously decreases, which leads to the need for high-density packaging techniques with high numbers of power and signal lines. By applying wireless power transfer technology at the printed circuit board (PCB) and package levels, the number of power pins can be greatly reduced to produce more space for signal pins and other components in the system. For the first time, in this paper, we propose and demonstrate a high-efficiency PCB- and package-level wireless power transfer interconnection scheme. We enhance the efficiency by applying magnetic field resonance coupling using a matching capacitor. The proposed scheme can replace a high number of power interconnections with rectangular spiral coils to wirelessly transfer power from the source to the receiver at the PCB and package levels. The equivalent circuit model is suggested with analytic equations, which is then analyzed to optimize the test vehicle design. For the experimental verification of the suggested model, the $Z$ -parameter results obtained from the model-based equation and measurement of the designed and fabricated test vehicles are compared at up to 1 GHz. The power transfer efficiency from the source coil to the receiver coil in this scheme is able to reach 85.6%. Finally, we designed and fabricated a CMOS full-bridge rectifier and mounted it on the receiver board to convert the transferred voltage from ac voltage to dc voltage. A measured dc voltage of 2.0 V is sufficient to operate the circuit, which generally consists of 1.5 V devices.</P>