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Partially Parallel Encoder Architecture for Long Polar Codes
Hoyoung Yoo,In-Cheol Park IEEE 2015 IEEE transactions on circuits and systems. a publi Vol.62 No.3
<P>Due to the channel achieving property, the polar code has become one of the most favorable error-correcting codes. As the polar code achieves the property asymptotically, however, it should be long enough to have a good error-correcting performance. Although the previous fully parallel encoder is intuitive and easy to implement, it is not suitable for long polar codes because of the huge hardware complexity required. In this brief, we analyze the encoding process in the viewpoint of very-large-scale integration implementation and propose a new efficient encoder architecture that is adequate for long polar codes and effective in alleviating the hardware complexity. As the proposed encoder allows high-throughput encoding with small hardware complexity, it can be systematically applied to the design of any polar code and to any level of parallelism.</P>
Energy-efficient Key-equation Solving Algorithm for BCH Decoding
Hoyoung Yoo,Youngjoo Lee 대한전자공학회 2018 Journal of semiconductor technology and science Vol.18 No.4
This paper presents an energy-efficient method to solve the key equation in BCH decoding. The key-equation solving block is so complicated that it consumes lots of energy because of multiple registers being dynamically updated every cycle. The block dominates the overall energy dissipation of strong BCH decoding and induces unwanted hotspots. In achieving a high-performance BCH decoder, an energy-efficient algorithm should be developed for solving the key equation. This paper proposes a novel method to detect the case of single error by exploiting the relation among syndromes. If a single-error case is detected, the modified error-locator polynomial is obtained without solving the key-equation. For a (16383, 15543, 60) decoder implemented in a 130nm CMOS process, the proposed method saves 99% and 91% of energy compared to the conventional algorithm and the previous method that detects the error-free case, respectively.
Low-Power Parallel Chien Search Architecture Using a Two-Step Approach
Hoyoung Yoo,Youngjoo Lee,In-Cheol Park IEEE 2016 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.63 No.3
<P>This brief proposes a new power-efficient Chien search (CS) architecture for parallel Bose-Chaudhuri-Hocquenghem (BCH) codes. For syndrome-based decoding, the CS plays a significant role in finding error locations, but exhaustive computation incurs a huge waste of power consumption. In the proposed architecture, the searching process is decomposed into two steps based on the binary matrix representation. Unlike the first step accessed every cycle, the second step is activated only when the first step is successful, resulting in remarkable power saving. Furthermore, an efficient architecture is presented to avoid the delay increase in critical paths caused by the two-step approach. Experimental results show that the proposed two-step architecture for the BCH (8752, 8192, 40) code saves power consumption by up to 50% compared with the conventional architecture.</P>
건강한 모바일 스토리지를 위한 초저전력 오류정정 시스템
유호영(Hoyoung Yoo),이영주(Youngjoo Lee) 대한전자공학회 2017 대한전자공학회 학술대회 Vol.2017 No.6
With the increase in the number of P/E cycles, the data integrity of recent NAND flash memories is seriously deteriorated, and the soft-decision error-correction codes (ECCs) are normally used to ensure the long-life of memories. For the energy-efficient mobile storages, however, it is necessary to extend the period of hard-decision ECCs rather than the soft-decision ECCs with power-starving sensing operations. In this paper, we introduce the concept of the healthy storages, and provide several ECC techniques that can prolong the healthy-life of NAND flash memories as long as possible, leading to the energy-efficient mobile storages.