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A Wide-gain-range Intermediate Frequency Integrated Circuit for a Superheterodyne Receiver
Changchun Zhang,Jingjian Zhang,Ying Zhang,Yi Zhang,Jie Liu,Sung Min Park 대한전자공학회 2018 Journal of semiconductor technology and science Vol.18 No.4
A wide-gain-range Intermediate Frequency (IF) integrated circuit is designed and implemented for a superheterodyne receiver in standard 0.18 μm CMOS technology. It consists mainly of a programmable attenuator, a Variable Gain Amplifier (VGA), a downconverting mixer and a fixed gain amplifier. The π-type-network attenuator is chosen over a T-type network one in order for a compact layout. The common-gate-input VGA is used for a high operation frequency, a small phase shift and a wide gain range. The common-gate Gilbert-type mixer with a dynamic current injection technique and a capacitive cross-coupling technique is employed for proper gain, low noise and high linearity. Furthermore, a Phase-Locked Loop (PLL) is also integrated monolithically so as to generate the desired local clock signal for the mixer. Measurement results show that, from an area of 2.16 mm×1.46 mm and power consumption of 234 mW, the IF chip is able to operate properly with a gain range of 5 dB ~ 57 dB, output power of above 0dBm, and so on. In addition, the on-chip local clock with an operation frequency of 660 MHz and a phase noise of -119.34 dBc @1 MHz is achieved.
A CMOS Dual-mode High-dynamic-range Wideband Receiver RF Front-end
Changchun Zhang,Yingjian Wu,Peng Zhang,Ying Zhang,Jie Liu,Sung Min Park 대한전자공학회 2018 Journal of semiconductor technology and science Vol.18 No.5
A dual-mode wideband high-dynamic-range receiver RF front-end consisting mainly of a low-noise amplifier (LNA) and a mixer is presented and implemented in standard 0.18 μm CMOS technology. Besides wideband input matching, the wideband LNA is optimized purposefully for low NF and high gain, and the mixer for high linearity and proper gain. In high-gain (HG) mode, with the LNA involved, the high sensitivity can be achieved; in low-gain (LG) mode, with the LNA bypassed, the mixer stands out and makes the front-end exhibit high linearity. In an overall view, the proposed dual-mode wideband RF front-end achieves a high dynamic range. With an occupied die area of 2360 μm× 1460 μm and a single supply voltage of 1.8V, measurement results show the dual-mode RF frontend can operate across the desired frequency range of 1.3 ~ 2 GHz and achieve gain of 20 dB and NF of 4.8dB in the HG mode, and average IIP3 of 8 dBm and P1dB of -4 dB in the LG mode, respectively.
A 2 GS/s, 6-bit DAC for UWB Applications In 0.18 ㎛ CMOS Technology
Yi Zhang,Zhonghua Liu,Changchun Zhang,Yufeng Guo,Ying Zhang,Xiaopeng Li,Youtao Zhang,Hao Gao 대한전자공학회 2019 Journal of semiconductor technology and science Vol.19 No.6
To satisfy higher and higher transmission rate and broadband requirement of modern communication, high-speed, low-resolution Digital-to-Analog Converters (DACs) becomes the key element. In this paper, the design of a 2 GS/s, 6 bit DAC without calibration for Ultra-wideband (UWB) applications, is presented. The DAC is based on current steering architecture and is segmented with 4 bit unary and 2 bit binary. To realize larger linear range and fast switching, the source degeneration switch is designed instead of the traditional differential switch. The DAC is designed and taped-out in SMIC 0.18 ㎜ CMOS technology and the area is 975 ㎛´ 775 ㎛. The wafer bonding measurement results shows that the DNL is 0.11 LSB, INL is 0.25 LSB. Under a clock frequency of 2 ㎓, the DAC can achieve a SFDR of 51 ㏈ for input signal of 6㎒, and a SFDR of 32.4 ㏈ for Nyquist input while the power consumption is 79 ㎽.
Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies
Zhang, Changchun,Li, Ming,Wang, Zhigong,Yin, Kuiying,Deng, Qing,Guo, Yufeng,Cao, Zhengjun,Liu, Leilei The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.4
Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard $0.18{\mu}m$ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.
A 15 GHz, <tex> $-$</tex>182 dBc/Hz/mW FOM, Rotary Traveling Wave VCO in 90 nm CMOS
Changchun Zhang,Zhigong Wang,Yan Zhao,Sung Min Park THE INSTITUTE OF ELECTRICAL ENGINEERS 2012 IEEE Microwave and Wireless Components Letters Vol. No.
<P>This letter presents a phase-noise-centric design methodology of a rotary traveling wave voltage controlled oscillator (RTW VCO). Based upon this methodology, a 15 GHz multiphase RTW VCO is realized in a standard 90 nm CMOS process. Particularly, shielded coplanar striplines are exploited to provide better shielding protection and higher characteristic impedance with comparable Q-factor than conventional coupled transmission lines. Measured results of the proposed RTW VCO demonstrates the frequency tuning range of 2 GHz, the output power level of 11.3 dBm, the phase noise of 109.6 dBc/Hz at 1 MHz offset, the clock RMS jitter of 2 , and the power dissipation of 12 mW from a single 1.2-V supply. The chip core occupies the area of 0.2 .</P>
A 15-GHz CMOS Multiphase Rotary Traveling-Wave Voltage-Controlled Oscillator
Zhang, Changchun,Wang, Zhigong,Zhao, Yan,Park, Sung-Min The Institute of Electronics and Information Engin 2012 Journal of semiconductor technology and science Vol.12 No.3
This paper presents a 15-GHz multiphase rotary traveling-wave voltage-controlled oscillator (RTW VCO) where a shielded coplanar stripline (CPS) is exploited to provide better shielding protection and lower phase noise at a moderate cost of characteristic impedance and power consumption. Test chips were implemented in a standard 90-nm CMOS process, demonstrating the measured results of 2-GHz frequency tuning range, -11.3-dBm output power, -109.6-dBc/Hz phase noise at 1-MHz offset, and 2-ps RMS clock jitter at 15 GHz. The chip core occupies the area of $0.2mm^2$ and dissipates 12 mW from a single 1.2-V supply.
A 15-㎓ CMOS Multiphase Rotary Traveling-Wave Voltage-Controlled Oscillator
Changchun Zhang,Zhigong Wang,Yan Zhao,Sung Min Park 대한전자공학회 2012 Journal of semiconductor technology and science Vol.12 No.3
This paper presents a 15-㎓ multiphase rotary traveling-wave voltage-controlled oscillator (RTW VCO) where a shielded coplanar stripline (CPS) is exploited to provide better shielding protection and lower phase noise at a moderate cost of characteristic impedance and power consumption. Test chips were implemented in a standard 90-㎚ CMOS process, demonstrating the measured results of 2-㎓ frequency tuning range, -11.3-㏈m output power, -109.6-㏈c/㎐ phase noise at 1-㎒ offset, and 2-ps RMS clock jitter at 15 ㎓. The chip core occupies the area of 0.2 ㎟ and dissipates 12 ㎽ from a single 1.2-V supply.
Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies
Changchun Zhang,Ming Li,Zhigong Wang,Kuiying Yin,Qing Deng,Yufeng Guo,Zhengjun Cao,Leilei Liu 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.4
Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and t재 fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard 0.18㎛ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.