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최우영(Wooyoung Choi),정현(Hyun Chung) (사)한국CDE학회 2013 한국 CAD/CAM 학회 학술발표회 논문집 Vol.2013 No.1
Welding is the primary joining process in manufacturing marine structures. As a way to improve the dimensional quality of products in shipyard during the production process, the welding distortion and their estimation have been studied rigorously. The welding distortion accounts for major geometrical variations in the intermediate products in shipbuilding processes and greatly affects the downstream assembly processes. The residual stresses, caused by the non-nominally shaped intermediate products, affect the magnitude of welding distortions as well. In previous research, an initial variation and welding distortion of the nominal parts are described as a linear superposition by the modified method of influence coefficient. However this research neglects the effects of the welding variations and residual stress to the final assembly spring-back deviation shape and only considers the mean deviation of welding distortion. This paper suggests a compliant assembly theory which includes the welding deformation using method of influence coefficient. The proposed model is based on the sources of variation and sensitivity matrix, which effectively represent the patterns of welding distortion of non-nominal plate parts. This suggested model is validated using the experimental data of thin plate welding.
디지털 로직을 통해 빠른 주파수 고정이 가능한 875MHZ Sub-Sampling 위상 고정 루프
최우영(Wooyoung Choi),안정모(Jungmo An),송준영(Junyoung Song) 대한전자공학회 2019 대한전자공학회 학술대회 Vol.2019 No.11
A Sub-Sampling Phase Locked Loop is a divider-less Phase Locked Loop. Which is used to create low noise output frequency. Conventional SSPLL is hard to utilize because of its narrow locking range. In our working by adopting digital block which implement binary searching algorithm solve the limitation of SSPLL and achieve much faster locking time than previous technology. In addition, using pulse control added Charge Pump, pass the signal only in certain time lead to decrease of noise in output frequency. Our SSPLL use 109.375MHz for REF clock and output frequency is 875MHz.