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신치훈(Chi-Hoon Shin),오명훈(Myeong-Hoon Oh),박경(Kyoung Park),김성운(Sung-Woon Kim) 대한전기학회 2006 정보 및 제어 심포지엄 논문집 Vol.2006 No.1
In this paper we present a new-generation sensor network processor which is not optimized in circuit level, but in system architecture level. The new design build on a conventional processor architecture, improving the design by focusing on application oriented specification, ISA, and micro-architectural optimization that reduce overall design size and advance energy-per-instruction. The design employs harvard architecture, 8-bit data paths, and an compact 19 bit wide RISC ISA. The design also features a unique interrupt handler which offloads periodical monitoring jobs from the main part of CPU. Our most efficient design is capable of running at 300 ㎑ (0.3 MIPS) while consuming only about few pJ/instruction.