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TSV 웨이퍼 공정용 Si<sub>3</sub>N<sub>4</sub> 후막 스트레스에 대한 공정특성 분석
강동현,구중모,고영돈,홍상진,Kang, Dong Hyun,Gu, Jung Mo,Ko, Young-Don,Hong, Sang Jeen 한국전기전자재료학회 2014 전기전자재료학회논문지 Vol.27 No.3
With the recent advent of through silicon via (TSV) technology, wafer level-TSV interconnection become feasible in high volume manufacturing. To increase the manufacturing productivity, it is required to develop equipment for backside passivation layer deposition for TSV wafer bonding process with high deposition rate and low film stress. In this research, we investigated the relationship between process parameters and the induced wafer stress of PECVD silicon nitride film on 300 mm wafers employing statistical and artificial intelligence modeling. We found that the film stress increases with increased RF power, but the pressure has inversely proportional to the stress. It is also observed that no significant stress change is observed when the gas flow rate is low.