SOI를 이용한 낮은 편광 손실차를 갖는 1×4 AWG에 관한 연구

林熙喆 명지대학교 1999 국내석사

본 논문에서는 SOI를 이용해서 낮은 편광 손실차를 갖는 1×4 AWG(arrayed waveguide grating)를 설계하였다. 유효굴절율법으로 SOI구조에서 도파로 폭과 식각깊이를 변화시켜 단일모드 구조와 최소의 편광차를 갖는 구조를 설계한 후 전산모의 하였다. 설계한 낮은 편광차를 갖는 단일모드 도파로 구조를 Cl2, He, SF6 gas를 이용해서 Reactive Ion Etching 방법으로 silicon을 식각해서 SOI 광도파로를 제작하였는데 gas의 유량, RF power, 압력을 변화시키면서 비등방도(anisotropy), 선택도(selectivity), uniformity를 고려한 최적의 gas조건을 찾았다. 도파로를 설계·제작한 조건을 이용해서 1×4 AWG의 도파로 폭과 식각깊이를 조절해서 전산모의 한 결과, 도파로 폭이 3[μm], etch depth는 2[μm]에서 편광에 따른 최대 파장 이동(TE/TM shift)은 0.02[nm]로 낮은 편광 특성을 나타냈으며 -30[dB] 이하의 crosstalk과 l[dB] 이하의 insertion loss를 얻었다. In this thesis, the design scheme, simulation and fabrication of the polarization independent 1×4 AWG was studied using SOI structure. First, this thesis presents the design parameters of SOI waveguide with a high index difference and a large cross section of 5 ㎛ as well as the fabrication of a single mode SOI ridge waveguide. At the wavelength of 1.55 /㎛, the measured profiles were well matched to the result of EIM and BPM simulation. And second, design and simulation were performed for the polarization independent 1×4 AWG using SOI structure, and peak wavelength shift of this device was 0.02nm by BPM simulation. The response of this device is shows the polarization independent characteristics.

Si 기판을 이용한 SOI MOSFET 제작

이기성 충북대학교 2014 국내석사

As the effective channel length of Si device is shrinking, the devices have faced problems such as increased leakage current, threshold voltage roll-off, and degradation of sub-threshold slope. Thus, MOSFET on thin Si body on insulator (SOI) has widely been utilized in past decade to reduce these short channel effects. In this study, we report on the fabrication results of a deep sub-micron MOSFET after converting a bulk Si substrate into SOI type structure as an alternative of SOI wafer. In order to separate thin top Si active layer from the underlying substrate, we processed the steps of channel definition, deep trench etch at both sides of channel, and thermal oxidation from the sides. The cross-sectional TEM examination indicated a SOI structure: V-shaped active layer with thickness less than 0.1μm floating on SiO2. Further fabrication processes of self-aligned S,D implant and contact formation yielded a sub-micron MOSFET. The device's threshold voltage with W/L=180nm/165nm was 0.22V, and the sub-threshold slope was unexpectedly large as 250mV/dec. The Id-Vd exhibited a linear relationship with variation of Vg due to the carrier velocity saturation in a sub-mircon MOSFET: . The device had also suffered from DIBL(Drain-Induced Barrier Lowering), showing the increased Id at high Vds with barrier lowering effect of ▵V ~ 630mV/V. Overall device performance was not outstanding probably inherited to the unscaled oxide thickness, tox=10nm, and the sidewall interface states in oxides surrounding the channel. It is however very meaningful that the SOI type structure was realized by using conventional bulk Si wafer and implemented for a sub-micron MOSFET.

Cl2-based neutral beam system을 이용한 silicon-on-insulator 웨이퍼의 표면조도 향상에 關한 硏究

민태홍 성균관대학교 일반대학원 2010 국내석사

반도체 산업에서 nano-scale device 또는 ultra-large-scale integration (ULSI) device를 제조함에 있어서 SOI (silicon on insulator) 구조를 이용한 기술은 빠른 성장세를 보이고 있다. High speed, high packing density, immunity from latch up, low power dissipation 그리고 high resistance to ionizing radiation 같은 장점을 가진 high quality의 SOI wafer를 제작하기 위해서 많은 노력이 이루어지고 있으며 특히 carrier의 이동도 향상을 위한 표면조도 개선이 중요하게 다루어지고 있다. 표면의 거칠기와 형태를 atomic scale로 향상시키기 위해서 고안된 일련의 방법들은 긴 공정시간과 정확한 두께조절의 신뢰성 부재와 같은 문제점을 안고 있다. 이에 따라 물리적, 전기적 손상이 없으면서 표면 거칠기 향상을 극대화 시키고 정확한 두께조절을 이루어 낼 수 있다면 nano scale의 소자를 제작함에 있어서 이전보다 확연히 향상된 소자특성을 볼 수 있을 것이다. 따라서 본 연구에서는 SOI wafer의 roughness를 향상시키기 위해 이전에 시도 되었던 것들보다 진보된 방법인 Low-Angle Forward-Reflected Neutral Beam Etching을 이용한 방법을 적용하였고 최고의 etch rate을 찾기 위하여 source power를 300 W로 고정시킨 상태에서 가스 유량을 변화시켜 15 sccm에서 고밀도 플라즈마를 얻을 수 있었고 그에 따라 빔 에너지를 100 eV – 500 eV로 변화시켰을 때 500 eV에서 가장 높은 etch rate을 얻을 수 있었다. 또한 etch rate이 커짐에 따라서 표면의 조도 향상에 있어서도 가장 두드러진 효과를 얻을 수 있었다. 이러한 중성빔과 이온빔 에칭 시스템으로 SOI를 식각한 뒤 HR-TEM으로 물리적 손상에 대한 영향을 관찰해 보았다. Reference SOI의 경우 정상적인 Si 격자의 형상을 띄고 있었으며 중성빔 500 eV로 2분 30초를 식각하였을 경우에도 물리적 손상은 발생하지 않았다. 하지만 이온빔 500 eV로 1분 10초를 식각한 결과는 극 표면 층에서 물리적 손상이 발생하여 격자의 변화가 있었음을 확인할 수 있었다. 이 결과는 각각의 샘플을 NMOSFET으로 만든 소자에 있어서도 그대로 반영되어 probe station을 통해 transfer curve를 측정하여 carrier mobility를 측정한 결과 또한 중성빔으로 식각을 진행한 경우가 이온빔의 경우보다 2배 정도 빠른 mobility를 나타내었다. 위와 같은 결과를 통하여 차세대 반도체에서 쓰여질 ultra thin body SOI 웨이퍼의 top silicon layer 두께조절과 표면조도 향상을 중성빔을 통하여 이루어내어 더욱더 질 높은 소자 특성의 향상을 이룩할 수 있을 것으로 사료된다. For the next generation silicon substrates applied to nano-scale semiconductor devices, silicon-on-insulator (SOI) wafer is known to be one of the outstanding candidates because of the advantages such as high speed, high packing density, immunity from latch-up, low power dissipation, high resistance to ionizing radiation, etc. For the SOI wafer, the surface roughness of SOI wafer is very important because it can change the physical and chemical properties of the top silicon layer of the SOI wafer. Many approaches have been attempted to reduce the surface roughness of the SOI wafer by chemical mechanical polishing, high temperature annealing, wet etching, etc. but these methods are known to have some problems such as long processing time, reliability of exact thickness control, etc. In this study SOI wafers were etched by a chlorine neutral beam obtained by the low angle forward reflection of an ion beam and the surface roughness of the etched wafers was compared with that of the SOI wafers etched by a chlorine ion beam. The result showed that the surface roughness of the SOI wafer etched by the chlorine neutral beam was significantly improved compared to that etched by the chlorine ion beam. By etching about 190nm silicon of about 270nmthick top silicon layer of SOI wafer using the chlorine neutral beam, the rms surface roughness lower than 1.5 Å could be obtained with the etch rate of about 750 Å /min while that etched by the chlorine ion beam showed the rms surface roughness higher than 2.5 Å. The induced defects in the surface area of the SOI wafer by the ion beam and neutral beam were observed by high-resolution transmission-electron-microscopy(HR-TEM). An atomic force microscopy(AFM) was employed to measure and evaluated the surface roughness of the SOI wafer before and after the etching process, respectively. Finally we make the n-type MOSFET then confirm the mobility of SOI etched by neutral beam compare to ion beam.

(100) Si과 4˚ off (100) Si 웨이퍼를 이용한 직접접합 SOI의 제조 및 특성

유연혁 연세대학교 대학원 2000 국내석사

SOI(silicon on insulator)를 (100) 실리콘 기판과 4˚ off (100) 실리콘 기판을 이용하여 직접접합(direct bonding) 법으로 제조하였다. 먼저 (100) 실리콘 기판과 4˚ off (100) 실리콘 기판에 대한 산화거동, 산화적층결함과 C-V 특성에 관하며 고찰하였다. 4˚ off (100) 실리콘 기판이 (100) 실리콘 기판보다 산화속도가 빨랐다. 산화적층결함은 산화온도와 시간에 따라 성장하였으며 고온에서는 재수축하였고, 결함의 크기는 4˚ off (100) 실리콘 기판이 (100) 실리콘 기판보다 작았다. C-V 특성은 산화온도가 증가할수록 flat band voltage는 양의 방향으로 이동하였고 4˚ off (100) 실리콘 기판의 계면고정전하밀도가 (100) 실리콘 기판보다 작았다. 한편 수정된 SC-1(MSC-1)에 의해 형성된 chemical oxide를 XPS, Angular meter, AFM으로 분석하였는데, MSC-1 처리 시간이 길어질수록 형성된 chemical oxide의 두께와 친수화도는 일정하게 유지되었지만 표면 미세 거칠기는 증가하였다. 즉, (100) 실리콘 기판과 4˚ off (100) 실리콘 기판 모두에 대해 접합을 위한 MSC-1 최적의 처리 시간은 2분임을 알 수 있었다. 다음으로 접합된 SOI 구조를 여러 온도에서 열처리를 행하였다. (100) 실리콘 기판과 4˚ off (100) 실리콘 기판으로 제조된 SOI의 접합 강도는 1100℃ 열처리를 하였을 때 측정한계치인 10MPa 보다 크게 나타났다. 적외선투과카메라로 접합영역과 미접합 영역을 확인하였는데 열처리에 따른 접합영역의 변화는 없었다. 산화막을 제거하고 화학적 식각을 통해 접합 계면과 산화 계면에서 결함을 관찰한 결과 접합 영역에서는 결함이 응집되려는 현상이 관찰된 반면, 미접합 영역에서는 일반적인 산화공정에서 발견되는 결함이 관찰되었다. 그리고, (100) 실리콘 기판과 4˚ off (100) 실리콘 기판으로 제조된 SOI의 C-V 특성은 전형적인 MOS-capacitor의 특성을 나타내었다. SOI(silicon-on-insulator) was fabricated through the direct bonding using (100) Si and 4˚ off (100) Si wafer. At first, (100) Si and 4˚ off (100) Si wafer were oxidized in wet O_(2) and the oxidation kinetics, oxidation-induced stacking fault(OSF), C-V characteristics were investigated. The oxidation rate of 4˚off (100) Si was faster than that of (100) Si and OSF grew as the oxidation time and temperature increased and retrogrew at high temperature eventually. Also, he OSF length of 4˚ off (100) Si was smaller than that of (100) Si. C-V characteristic with oxidation temperature showed that flat band voltages were shifted positively, Fixed surface state charge density of 4˚ off (100) Si was lower than that of (100) Si. Then, the chemical oxide formed by treating the modified SC-1(MSC-1) on (100) Si and 4˚ off (100) Si wafer were investigated by XPS, Angular meter and AFM. As treatment time of the modified SC-1 solution increased, the chemical oxide thickness and the surface hydrophilicity were saturated but surface microroughness increased. The optimum surface modified condition for both (100) Si and 4˚ off (100) Si wafer were for 2 min under the modified SC-1 solution. Next, the wafers were directly bonded to form SOI structure and were annealed at various temperature. Bonding strength of both SOI structure using (100) Si and 4˚ off (100) Si wafer was increased over measurement limit(10mpa) at 1100℃ annealing. With the use of the transmission IR camera, the bonded and the void region were founded and the bonded region was not changed after annealing. By removing oxide film with chemical etching, it was possible to examine the stacking faults on the bonding and the oxidation interface. While the stacking faults of the bonded region were shown anomalies in the OSF gettering, those of the void region were silmilar to the results of thermal oxide, C-V characteristic of both SOI using (100) Si and 4˚ off (100) Si wafer also indicated similar characteristic of MOS-capacitor.

SOI 기판위에 제작된 광검출기의 전기적·광학적 특성에 관한 연구

김종준 建國大學校 2002 국내박사

In this dissertation, a new Silicon on Insulator (SOI)-based photodetector has been proposed with its basic operation principle explained. Fabrication steps of the detector are compatible with those of conventional SOI CMOS technology. With the proposed structure, RGB (Read, Green, Blue) colors, which are three primary colors of light, can be realized without using any organic color filters. To see the optical response, photodiodes formed on SOI and bulk Si wafers were simulated as parameters of polysilicon thickness and Si film thickness. It was shown that the characteristics of the SOI-based detector are better than those of bulk-based detector in terms of sharpness of optical spectrum because the buried oxide (BOX) in SOI wafer suppresses mixing of RGB colors. To see the response characteristics to the green (G) color among RGB colors, SOI and bulk NMOSFETs were fabricated using 1.5 ㎛ CMOS technology and characterized. We obtained optimum optical response characteristics at V_GS=0.35 V in SOI NMOSFET with the threshold voltage of 0.72 V. For the given light with the intensity of 0.8 mW/㎠ and the wavelength of 550 nm, SOI NMOSFET photocell shown signal amplification larger than 250 around V_GS of 0.35 V. Drain bias should be less than about 1.5 V to avoid any problem from floating body effect, since the body of the SOI NMOSFET was floated. Optical response of the photo cell with back gate bias was also studied. The ratio of drain current with light to drain current without light becomes small as the back channel is turned on. The SOI and the bulk NMOSFETs shown maximum drain currents at the wavelengths of incident light around 550 nm and 750 nm, respectively. Therefore the SOI detector is more suitable for the G color detector.

SIMOX SOI 構造의 製造 및 特性分析

배영호 慶北大學校 大學院 1992 국내박사

SIMOX SOI structures are fabricated under various conditions and characterized electrically and physically to establish a characterization technology which is a key to the fabrication of high quality SIMOX SOI. The first subject of this work is to investigate the annealing condition dependence of the characteristics of SIMOX SOI. SOI structures are fabricated under various annealing conditions. The microstructure and the behavior of oxygen atoms during annealing process are investigated through AES/TEM analysis. The crystalline quality of the structures is examined through transmission electron diffraction experiments. The electrical properties are measured by SRP and MOS C-V technique. Reduction of oxygen concentration in the SOI layer is dominated by the behavior of oxygen precipitates. The electrical properties of the structures are influenced by oxygen precipitates which initiate to desolve at the annealing temperature of 1250℃. The electrical properties of the structure are improved with the dissolution of oxygen precipitates. Dielectric and interface properties are also improved after annealing at high temperature. The second subject of the work is the examination of possibility of oxygen does reduction required for SIMOX fabrication. Characteristics of the SIMOX SOI formed by subcritical oxygen dose is investigated using physical methods such as AES, XPS and TEM as well as electrical methods such as SRP and C-V. Although oxygen dose is 0.4×10^(18)/㎠ which corresponds to below one third of critical dose, a continuous buried oxide layer can be obtained while no oxygen precipitates and crystal defects are found in the SOI layer. In the case of the dose of 0.8×10^(18)/㎠, there are numerous Si precipitates in the buried oxide layer. But dielectric properties of the buried oxide layer is fairly good. The third subject is electrical characterization of SOI structures. A method for characterization of both SOI/buried oxide and buried oxide/substrate interfaces is suggested. The C-V analysis of SIS capacitors is based upon conventional MOS C-V theory. SIS capacitors are fabricated using SIMOX SOI wafers. Complete depletion of the SOI layer is prevented by increasing either SOI layer thickness through epitaxial growth or doping concentration of the layer. High and low frequency C-V measurements are conducted using conventional method. Parameters such as buried oxide thickness, doping concentration, interface trap density are determined by the measurements.

직접접합법에 의해 제조된 SOI의 계면 결함에 관한 연구

김규태 연세대학교 대학원 2001 국내석사

(100) 실리콘과 SiO_(2) 열 산화 박막을 이용하여 직접접합법(wafer direct bonding method)으로 SOI(silicon-on-insulator)를 제조할 경우 Si/SiO_(2) 계면에 나타나는 결함에 대하여 연구하였다. 상온에서 직접접합을 하기위해 MSC-1(modified SC-1)용액으로 친수화 처리를 하였으며, wetting angle 및 AFM(atomic force microscopy) 측정을 통하여 최적의 친수화 처리 시간이 2분임을 알았다. 후 열처리시 발생하는 응력의 크기 및 후 열처리 온도와 시간 변화가 SOI의 계면에 존재하는 산화적층결함의 응집 거동에 미치는 영향을 관찰하기 위해 상온에서 접합된 SOI 시편에 대해 후 열처리 공정을 행하였다. 접합 영역의 경우 500℃ 후 열처리 공정을 수행한 후 Si/SiO_(2)계면에 존재하던 산화적층결함들이 응집하기 시작하였으며, 1200℃로 후 열처리 온도가 증가함에 따라 응집된 모양이 십자형에서 십자를 둘러싸는 환형으로 변하였다. 400℃의 경우 24시간 동안 후 열처리를 행하여도 산화적층결함이 응집되는 현상은 나타나지 않았으며, 600℃의 경우 후 열처리 시간이 30분에서 24시간으로 증가함에 따라 응집된 산화적층결함의 평균 크기 및 밀도는 약간 증가하였지만, 응집된 모양은 변하지 않았다. 상부 실리콘을 박막화한 경우와 로냉한 경우 산화적층결함의 응집 거동은 일반적인 후 열처리 공정시 나타나는 결과와 동일한 경향을 나타내었다. 이로부터 후 열처리시 나타나는 응집된 산화적층결함들의 모양은 2개의 전이 온도를 기준으로 그 모양이 변하며, 이러한 모양의 변화는 후 열처리 시간과 계면에 존재하는 응력의 크기보다는 후 열처리온도에 의해 결정된다는 것을 알 수 있었다. 후 열처리 온도가 높아짐에 따라 직접접합된 SOI를 이용하여 제작한 MOS-capacitor의 누설전류 밀도는 증가하였다. The interfacial defects of a directly bonded SOI(silicon on insulator) structure were studied. At first, the kinetics of the thermal oxidation of silicon and the stacking fault distributions at the oxidation interface were investigated. The OSFs(oxidation induced stacking faults) grew as the oxidation temperature and time increased and retrogrew at high temperature eventually. The chemical oxide formed by treating the MSC-1(modified SC-1) on (100) Si wafer was investigated by Angular meter and AFM. The optimum surface treating time for wafer direct bonding was 2min. In order to investigate the effect of annealing temperature, time and thermal strain caused by annealing process on gettering behavior of OSFs at the S/SiO_2 Interface of SOI structure, the directly bonded SOI structures were annealed. The OSFs existed in bonded region started to getter at the annealing temperature of 500℃ and then the OSFs gettered as the pattern of a cross in the case of 800℃. The gettered OSFs with a cross pattern align in the <110> direction. The pattern of gettered OSFs was developed from a cross to a circle around the cross, with the increase of the annealing temperature to 1200℃. At 400℃ annealing temperature, gettering behavior of OSFs did not happen even if the annealing process was performed during 24hours. The basic pattern of gettered OSFs was not changed although the annealing process is carried out for 24hours at 600℃. On the other hand, the average size and density of gettered OSFs was slightly increased as the annealing time lengthened. The general gettering behaviors of OSFs were also observed in the case of furnace cooling and that upper silicon layer thickness is about 1004m. From these results, it was found that the gettering behaviors of OSFs has two transitional temperature in the pattern and the pattern of gettered OSFs was not determined by the annealing time and thermal strain but the annealing temperature. The leakage current density of buried oxide layers increased from 8.5×10^(-4) A/㎠ to 7×10(-3) A/㎠, when the annealing temperature increased from 300℃ to 1200℃.

Al_(2)O_(3)매몰층이 형성된 접합 SOI 기판의 제조 및 특성평가에 관한 연구

최승우 高麗大學校 大學院 2002 국내박사

In the past decade, SOI(silicon-on-insulator) structures have been investigated for various device applications, such as three-dimensional integrated circuits, power devices, higher immunity to radiation, novel TFT(thin-film-transistor) devices and micromachining technologies. Because SOI has solved for the problems of bulk silicon devices associated with junction area, leakage, isolation, and capacitance, SOI has become an attractive technology for future generations of mainstream VLSI products. However, with increasing power dissipation it is becoming more and more of a problem to transfer the heat from the active region of the circuits to the heat sink. For SOI, the situation is even worse than in bulk technology due to the poor thermal conductivity of the buried insulator. SOI buried layers must have some basic properties for the power integrated circuits application including low leakage current and high breakdown voltage as well as high thermal conductivity. My studies have found new buried oxide layer materials for those applications by replacing silicon dioxide with alumina. I made SOI wafers having alumina buried layers by the wafer direct bonding method. For satisfying the requirement of the bonding process, I deposited an alumina layer by ALD (Atomic Layer Deposition) with TMA (trimethylaluminum, Al(CH_(3))_(3)) and water (H_(2)O). We confirmed that the deposited alumina film had good stoichiometry through the film depth and low roughness, which is an indispensible requirement in the wafer bonding process by AES(Auger Electron Spectroscopy) and AFM (Atomic Force Microscopy). For the fabrication of the SOI wafer, I utilized oxygen plasma surface treatment for wafer bonding and investigated the effect on the silicon and alumina surfaces. The influence of process parameters such as RF power and plasma exposure time on the surface energy, surface cleanliness and roughness were investigated by the contact angle method, AES and AFM. The oxygen plasma surface treatment rendered high surface energy having high polarity by modifying surface structure and removing impurities like hydrocarbon, which showed this treatment was an effective method for wafer direct bonding for SOI wafers. In my experiment, the trade-off between surface activation and roughness was required to improve the bonding area and the bonding energy because the excessive RF power or plasma exposure time could degrade the bonding quality. We activated the alumina and silicon surfaces by the oxygen plasma treatment in the condition of 70 W RF power and 60 sec. of plasma exposure time, which resulted in a sufficient bonding strength with no voids for SOI fabrication. The results from the electrical characterization of the Al_(2)O_(3) films show that from the leakage and breakdown considerations, the Al_(2)O_(3) films are of sufficient quality to be used as the buried insulator of SOI-materials. The thermal conductivity of Al_(2)O_(3) is much lower than that of SiO_(2), which can solve the problem of self-heating effect in SOI power devices by effectively transferring the heat to silicon substrates. By using the oxygen plasma surface treatment, I successfully fabricated the bonded SOI wafers with in Al_(2)O_(3) buried layer that has a higher breakdown voltage, lower leakage current and higher thermal conductivity than those of a SiO_(2) buried layer.

LA QUESTION DU SUJET CHEZ PAUL RICCEUR

Yun, Seong Woo Universite Paris XII-Val de Marne 2002 해외박사

RESUME : L’etude de ≪ la question du sujet ≫ chez Paul Ricœur, que nous essayons de realiser dans le present travail, se construit autour de trois grands axes: la dimension corporelle, la dimension langagiere, et la dimension interpersonnelle et institutionnelle du sujet. La dimension corporelle du sujet s’appuie sur la lecture suivie du volontaire et l’involontaire, pour penser le sujet incarne, a partir de la critique de la Cogito deracine. La dimension langagiere du sujet se developpe, de La symbole du mal, a De l’interpretation. Essai sur Freud, Le conflit des interpretations et la Metaphore vive, et enfin jusqu’a Temps et recit et Du texte a l’action, sans jamais oublier les monographies importantes de l’auteur. D’ou le sujet mediatise, ou soi instruit, a partir de la critique du Cogito immediat. La dimension interpersonnelle et institutionnelle et institutionnelle du sujet procede de la lecture croisee de Soi-meme comme un autre en rapport avec les ecrits precedents et suivants. Enfin cette etude aboutit a la question de savoir ce que veulent dire le corps, le langage, l’autre et l’institution pour le sujet : ils designent, disons nous, la mediation, c’est-a-dire, si on prend le mot en son sens le plus fort, la condition. TITRE en anglais : The Question of The Subject at Paul Ricœur Summary : The study of ≪ the question of the subject ≫ at Paul Ricoeur, that we try to carry out in this work, is built around three large axes: body dimension, linguistic dimension, and interpersonal and institutional dimension of the subject. The body dimension of the subject supports on the reading followed by Freedom and Nature, to think the incarnated subject, starting from the critic of uprooted Cogito. The linguistic dimension of the subject develops, from The Symbolism of Evil, via Freud and Philosophy, The Conflict of Interpretations and The Rule of Metaphor, and finally at Time and Narrative and From Text to Action, without never forgetting the significant monographs of the author. From where the mediatized subject, or informed oneself, starting from the critic of immediate Cogito. The interpersonal and institutional dimension of the subject proceeds of the cross reading of Oneself as Another in connection with the preceding and following writings. Finally this study leads to the question of knowing what wants to say the body, the language, the another and institution for the subject: they indicate, the mediation, if one takes the word in his direction most extremely, the condition.

SOI 및 sSOI 웨이퍼를 이용한 반도체 쇼트키 접합의 전기적 구조적 특성 분석

서민우 전북대학교 일반대학원 2013 국내석사

We fabricated Er-silicide (ErSi1.7) Schottky contacts to strained silicon-on insulator (SSOI) with a strain level of 0.77% and silicon-on insulator (SOI) investigated their structure and electrical properties in the temperature range of 225 - 400 K. The Schottky parameters such as the barrier height, ideality factor, and series resistance were found to strongly depend on temperature. Barrier height and ideality factor were found to decrease and increase, respectively, with decreasing temperature. The series resistance gradually increased with decreasing temperature. A discrepancy between the Schottky barrier heights calculated from the forward current-voltage (I-V) characteristics and Norde’s method indicated a deviation from the ideal thermionic emission of ErSi1.7/SOI and sSOI Schottky diode. The lateral inhomogeneity of the schottky barrier and potential fluctuations at the interface between ErSi1.7 and SOI/sSOI could be a main cause of the difference between the calculated and theoretical values of the Richardson constant. On the basis of a thermionic emission mechanism with a Gaussian distribution of the barrier heights, temperature dependency of ErSi1.7 Schottky contact to SOI and sSOI was explained in terms of the barrier height inhomogeneities at the interface.