An Inductor-First Hybrid Step-Down DC-DC Converter For Battery-Powered Devices : 배터리 구동 장치를 위한 하이브리드 스텝-다운 DC-DC 컨버터

신민아 경북대학교 대학원 2025 국내석사

An Inductor-First Hybrid Step-Down DC-DC Converter For Battery Charger Applications In modern power conversion systems, miniaturization and high integration have become critical challenges in electronic device design. As electronic devices become increasingly compact and multifunctional, the space available for internal components is severely constrained. Inductors play a crucial role in power conversion efficiency, but their physical size and characteristics pose significant challenges for miniaturization and integration. When high inductance is required, the size and volume of the inductor increase, leading to efficiency degradation and performance issues. To address these challenges, various design techniques have been proposed, including the utilization of parasitic inductance from cables and the use of on-chip inductors. However, parasitic inductance can introduce instability due to environmental changes, and on-chip inductors often suffer from higher resistance, leading to increased conduction losses. Conversely, discrete inductors provide lower resistance, minimizing conduction losses, but their application is limited in miniaturized environments like mobile devices. This study proposes a solution to these issues by introducing a hybrid step-down DC-DC converter architecture that places the inductor at the input stage rather than the output stage. This approach uses three power switches, which reduces the inductor current ripple and enhances efficiency compared to traditional buck converters. Experimental results show that the proposed design achieves a higher efficiency compared to previous research. Implemented using only 180nm CMOS technology, the design offers benefits such as reduced production costs and compatibility with existing CMOS-based circuits, while maintaining high integration and miniaturization. This research presents a novel design approach that reduces dependence on inductors and maximizes efficiency and performance in miniaturized, high-integration power conversion systems. Key words : Inductor, Input, Hybrid DC-DC Converter, Inductor current ripple, Battery charger, CMOS, Miniaturization.

Wireless transcutaneous power transmission using integrated flexible inductors

서정훈 Graduate School, Yonsei University 2007 국내석사

Most existing implantable medical devises need electrical power. But, it could not work in one’s life because of limitation of battery capacity. Therefore, the integrated flexible inductor was designed for wireless transcutaneous power transmission to implanted medical devices. Unlike the conventional wireless power transmission methods which use a thick or inflexible inductor, the realized method use a mechanically flexible inductor which can be less invasively implanted and easily attached to human body.The inductor pair uses for wireless power transmission. The primary inductor is attached on the patient’s skin and the secondary inductor is implanted under the subcutaneous tissue. Two inductors has same pattern such as line space and width. When a signal is inputted to the primary inductor, the signal generates magnetic flux from the primary inductor to the secondary inductor. And then, the magnetic flux induces signal into the secondary inductor which is called electromagnetic induction effect. The transmission efficiency is decided by the induced magnetic flux to the secondary inductor. To increase the magnetic flux density between two inductors, core material is widely used in transformer. In this study, a permalloy which is alloyed nickel 81 % and iron 19 % is used because high permeability and easy fabrication process.Three kinds of flexible inductor are fabricated by using FPCB fabrication method. One is air core, another is plate core and the other is pot core type. Polyimide is used for substrate and copper is used for inductor line and seed layer for permalloy plating. The differences of transmission efficiency along inductor feature are measured by using function generator and oscilloscope. The skin and subcutaneous tissue of canine is used for confirming the transmission efficiency and the side effect when it implanted.

Active Inductor를 이용한 능동 대역 통과 필터의 설계 및 제작

이기훈 전남대학교 대학원 2002 국내석사

본 논문에서는 AI(Active Inductor)를 이용하여 1MT-2000 대역에서 적용할 수 있는 능동 대역 통과 필터를 설계 및 제작하였다. 먼저 Chebyshev 다항식을 이용하여 이상적인 L-C필터를 설계한 후 이를 공전기 형태로 변환하여 병렬 인덕턴스를 구하고 이를 Single P-HEMT의 간단한 구조로 구현하였다. 이상적인 Inductor와 비교했을 때 적은 저항 값만을 포함한 Active Inductor를 구현하였고 실제 상용 제품보다 넓은 주파수 범위에서 Inductor로 동작하는 이상적인 Inductor에 유사한 주파수 특성을 확인하였다. 초고주파 회로설계 소프트웨어인 ADS (Advanced Design System)를 이용하여 회로를 설계하고 최적화 한 후 전체 회로 제작은 비유전율 3.38 두께 0.58 mm 인 Teflon 기간 상에 MIC(Microwave Integrated Circuit) 형태로 제작하였다. 실제 제작, 측정한 결과 1.91 GHz와 2.1 GHz에서 각각 -34 dB, -35 dB, 중심 주파수인 1.95 GHz에서 삽입손실 -5.4 dB의 IMT-2000 대역에서 적용 가능한 대역통과 필터의 특성을 얻었고 Two - Tone Test로 선형성을 검증하여 Intermodulation Distortion에 의한 3차항이 원 신호에 비해 -55dB 의 억압이 되는 선형적인 특성을 확인하였다. Abstract In this paper, Active Band Pass Filter using AI (Active Inductor) is designed and fabricated. Active Inductor represented 1.74 nH inductance only using Single P- HEMT (Psedomorphic High Electron Mobility:ATF- 34143 producted by Agilent) and its characteristics are similiar to ideal 1.74 nH inductor, The whole circuit was fabricated on the Teflon substrate( ε,=3.38, T=078mm) using a microstrip line and ADS(Advanced Design System) was used in order to design and optimize. the results between simulation and measurement of Active Band Pass Filter have good agreements. The results indicate that Active Band Pass Filter using AI (Active Inductor) adequate for recievers of IMT-2000 User Equipments.

디지털 CMOS 공정을 이용한 3차원 솔레노이드 인덕터 개발 및 VCO/PLL 적용에 대한 연구

남철 건국대학교 대학원 2011 국내박사

본 논문은 표준 디지털 CMOS 공정(Standard Digital CMOS Process)의 배선 금속(Metal)과 비아(Via)를 이용하여 Solenoid Inductor를 설계 및 제작하고 이를 이용하여 5 ~11 GHz 대역에서 동작하는 VCO(Voltage Controlled Oscillator)및 PLL(Phase Locked Loop)에 응용한 결과에 관한 논문이다. 기존 디지털 CMOS 공정에서, 수 GHz대역의 Ring-Oscillator기반 VCO의 높은 위상 잡음(Phase Noise)을 개선하기 위해 사용되는 LC VCO는, 디지털 CMOS 공정에서 제공하지 않은 Spiral Inductor를 직접 설계자가 설계해서 사용해야 하는 불편한 점과 높은 점유 면적을 차지하는 점을 개선할 필요가 있다. Solenoid Inductor는 표준 CMOS공정에서 제공하는 배선 금속 적층(Metal Stack)을 이용하여 기판에 수직한 구조물을 형성하고, 수평 한 방향으로 감은 수를 조절하는 간단한 방법으로, 설계가 용이하며 디자인 룰(Layout Design Rules)을 위반하지 않아 기존 공정과의 호환성을 유지한다. 또한 Solenoid Inductor의 자속(Magnetic Flux)은 기판(Substrate)에 평행하여 기판에서 와류 전류(Eddy Current)에 의한 손실이 적으므로 기판 손실을 줄이기 위한 폴리실리콘(Poly-Silicon)이나 배선 금속에 의한 Ground Shield가 필요하지 않아, 인덕터 밑에 수동 부품이나 배랙터(Varactor)등을 둘 수 있어(Circuit Under Inductor) 추가적인 면적 절약의 효과가 있다. Solenoid Inductor의 인덕턴스는 구조물 파라메터(Design Parameter)로 감은수(N)와 코어 단면적(AC)을 이용하여 선형적으로 예측 가능하며, 인덕턴스와 첨예도(Quality Factor)의 최적화 작업은 3-D EM(Electro-Magnetic) Simulator를 이용하여 가능하며, 전기적 특성으로 추출된 고주파 모델인 S-parameter는 VCO 및 PLL 회로 설계에 사용된다. Solenoid Inductor를 탑재한 VCO는 배랙터에 의한 성긴 튜닝(Coarse Tuning)으로 4 ~ 5 GHz 대역, 10 ~11 GHz 대역의 1 GHz 이상의 광 대역 동작이 가능하며, 시그마델타 모듈레이터(Sigma-Delta Modulator)를 사용하여 미세 성긴 튜닝(Fine Coarse Tuning)을 함으로서 수 KHz 단계의 미세 조정이 가능하다. 0.13 μm 1 Poly 6 Metal 표준 CMOS공정을 이용하여 구현된 Solenoid Inductor는 0.53~1.44 nH범위의 인덕턴스와 Q=5정도의 첨예도를 보였으며, 제안된 등가 모델로부터 구한 RS, LS 파라메터는 감은 수(N)에 대해 1차 식으로 근사 됨으로써, 제공 되지 않는 N값에 대한 인덕턴스를 예측하고, VCO의 동작 주파수까지 예측을 가능하게 하였다. 본 Solenoid Inductor를 내장한 PLL은 디지털 CMOS 공정에서 요구되는 수 GHz대역의 PLL에 적합하게 사용될 수 있을 뿐만 아니라, LNA, Mixer등 고주파 부품으로도 광범위하게 사용되어, 별도의 공정적인 비용을 요구하는 RF CMOS 공정을 사용해야 하는 경제적 부담을 덜 수 있다. This paper presents a 3-D solenoid inductor constructed by metal stack and its application to VCO and PLL using the digital CMOS process. The current spiral inductor based VCO which is used to overcome the high phase noise from the ring-oscillator based one is still challenging the circuit engineer to take risk of designing by himself and responsibility of its performance. What is worse, it occupies much area even a sub-nanometer process is progressing. On the contrary, a solenoid inductor is built by all metal and via layers vertically and expanded horizontally to the substrate so that the number of turn is adjusted. It is easy to design and meet the layout design rules keeping its compatibility with any digital CMOS process. Additionally, it is possible to place circuits under an inductor (CUI) since the horizontal magnetic flux doesn't require the ground shielding pattern to lower the substrate loss by the eddy current in substrate. The inductance and quality factor of a solenoid inductor is qualitatively estimated simply by the design parameters such as the number of turn (N) and magnetic core area (Ac) and quantitatively analyzed by 3-D EM (electro-magnetic) simulator. The extracted S-parameters from the EM simulation are used for suggesting the equivalent lumped model for a solenoid inductor. This model is used to the circuit simulation for designing a VCO (Voltage controlled oscillator). The solenoid inductor integrated VCO has the wide tuning range over 4 ~ 5 GHz and 10 ~11 GHz and the fine tuning step by virtue of the coarse tuning of a bunch of varactor bank and by sigma-delta modulator, respectively. A solenoid inductor implemented in 0.13 μm 1 Poly 6 Metal Standard CMOS process has the inductance of 0.53~1.44 nH and the quality factor of 5. The proposed 1st order model of RS and LS is useful to estimate the inductance of an inductor not in model library and its operating frequency of VCO. Finally, a solenoid integrated PLL is suitable for low cost and low power mobile application. Moreover, the solenoid inductor can be used for RF passive component for LNA and Mixed to save the cost without using the expensive RF CMOS process.

A Single-Inductor Multi-Path Multi-Stage Hybrid DC-DC Converter for High Efficiency with High DCR Inductor

박근태 경북대학교 대학원 2024 국내석사

모바일 환경에서 multiple inductor activation을 통한 multi-phase buck converter의 효율 개선

서경수 성균관대학교 일반대학원 2021 국내석사

현재 모바일 디바이스는 유저들에게 더 좋은 기능을 제공하기 위해 지속적인 performance 향상이 요구되면서 CPU / GPU 등의 core frequency가 계속해서 증가하고 있다. 이를 구동하기 위해 많은 Power가 필요하게 되었고 충분한 power 공급을 위해 multi-phase buck converter가 사용되고 있다. Buck converter는 switching regulator이기 때문에 phase의 output node마다 passive 소자인 inductor와 capacitor가 필요하다. 그 중에서도 inductor는 Size가 매우 큰 부품이기 때문에 PCB 공간에 제약이 많은 모바일 디바이스의 전체 실장 면적에서 많은 크기를 차지한다. 뿐만 아니라 voltage regulating을 하게 되면서 발생하는 power loss에서 많은 부분을 차지하고 있는 부분이 바로 inductor에서 발생하는 conduction loss이다. Inductor의 conduction loss를 줄이기 위해서는 inductor의 DCR 감소가 필요한데 이를 위해서는 inductor의 size 증가가 필요하다. 그렇기 때문에 PBA size에 민감한 모바일 환경에서는 inductor의 size를 키우는데 있어서 제약이 있을 수 밖에 없고, 현재는 약 3~40mΩ 의 DCR을 가지는 inductor를 사용하여서 많은 power가 inductor의 conduction loss로 소모된다. 그리고 multi-phase buck converter는 높은 효율을 제공하기 위해서 load current에 따라 동작하는 phase의 개수를 조절하는 방식을 사용하고 있는데 1개의 phase만 사용되는 light load 구간에서는 사용되지 않는 phase의 output node에 할당된 inductor가 많은 공간을 차지하면서 사용되지 않는다. 본 논문에서는 output inductor들 사이에 switch를 추가하고 1-phase만 동작하는 상황에서 해당 switch를 on시켜서 output node의 multiple inductor를 activation시켜서 current path를 추가하여 준다. 그로 인해 Inductor의 DCR이 절반 수준으로 감소하게 되고 이는 결국 inductor conduction loss를 저감하여 multi-phase buck converter의 효율이 개선된다. 본 논문은 MATLAB을 이용하여 simulation을 진행하였으며 simulation 결과를 보면 기존의 multi-phase buck converter 대비 2-phase cuck 에서는 약 1.7% 효율 향상을 보였고, 3-phase buck 에서는 약 2.4%의 효율 향상을 확인하였다. DC-DC conversion efficiency of the multi-phase buck converter in mobile environment is improved by activating multiple inductors during magnetization phase. Thanks to the parasitic resistance reduction in inductors, multiple inductor activation achieves up to 1.7% efficiency improvement compared to conventional variable phase buck converter.

The Dual-winding Three-Phase Common-Mode inductor: Modeling and Experimental Validation

왕산산 건국대학교 대학원 2024 국내박사

Three-phase common mode (CM) inductors are widely used in motor drives to limit ground currents, axial voltages, and EMI emissions. With the help of high-performance switching devices such as SiC MOSFETs, the switching frequency of power converters is increasing, and the role of common mode inductors is becoming more and more critical. This paper considers four levels for modelling three-phase inductors: common mode inductance, core losses, winding losses, and parasitic capacitance. Moreover, the leakage inductance of the three common mode inductors is described in detail from the solution path to the solution method. Regarding the saturation problem of inductors, a simple estimation can be made by the leakage inductance, which can avoid the saturation problem of the iron core. Because the parasitic capacitance greatly influences the inductance, the winding of the inductor is a double winding, and the centre tap is used, which can increase the coupling coefficient and reduce the leakage inductance. Three-phase common-mode parasitic capacitance has a turn-to-turn capacitance, turn-core capacitance and winding capacitance, which can be equated to turn-turn capacitance and turn-core capacitance into C_a, turn-core capacitance and winding capacitance can be equated to C_N when the common-mode signal through the common-mode inductors there will not be a signal flowing through the parasitic capacitance of the two windings, so the Cn can be not to be taken into account. The parasitic capacitance is only C_a. In order to eliminate the parasitic capacitance, the centre tap of the inductor is connected to an external capacitor that is about four times larger than the parasitic capacitance and the resonant frequency of the impedance is made more significant by comparing the insertion voltage gain using the PSM1735; by using the double-winding common-mode inductors to build the EMI filter, the results prove that, although a relatively large capacitance is introduced, the parasitic capacitance of the inductors themselves is It is proved that the parasitic capacitance of the inductor itself is significantly eliminated. Moreover, the filter constructed by the dual-winding common-mode inductor is placed in the three-phase inverter circuit, and the filtering effect is better than that of the traditional three-phase common-mode inductor. Thus, the proposed dual-winding three-phase common-mode inductor can reduce the effect of capacitance on the inductor through the particular winding method. 3상 공통 모드(CM) 인덕터는 지면 전류, 축전압 및 EMI 방출을 제한하기 위해 모터 드라이브에서 널리 사용됩니다. SiC MOSFET와 같은 고성능 스위칭 장치의 도움으로 전력 변환기의 스위칭 주파수가 증가하면서 공통 모드 인덕터의 역할은 더욱 중요해지고 있습니다. 본 논문에서는 3상 인덕터 모델링을 위해 고려되는 네 가지 수준을 고려합니다: 공통 모드 인덕턴스, 코어 손실, 감손 손실 및 기생용량. 또한, 세 개의 공통 모드 인덕터의 누설 인덕턴스가 해결 경로에서 해결 방법까지 자세히 설명됩니다. 인덕터의 포화 문제에 대해서는 누설 인덕턴스를 사용하여 간단한 추정이 가능하며, 이는 철자의 포화 문제를 피할 수 있습니다. 기생용량이 인덕턴스에 큰 영향을 미치기 때문에 인덕터의 감은 두 배 감으로 되어 있으며 중앙 탭이 사용되어 결합 계수를 증가시키고 누설 인덕턴스를 감소시킬 수 있습니다. 3상 공통 모드 기생용량은 턴 투 턴용량, 턴 코어용량 및 와인딩용량이 있으며, 턴 투 턴용량과 턴 코어용량을C_a로 간주할 수 있습니다. 턴 코어용량과 와인딩용량은으로 간주할 수 있습니다. 공통 모드 신호가 공통 모드 인덕터를 통과할 때 두 와인딩의 기생용량을 통과하는 신호는 없으므로C_N은 고려하지 않아도 됩니다. 기생용량은 단지C_a입니다. 기생용량을 제거하기 위해 인덕터의 중앙 탭은 기생용량보다 약 네 배 큰 외부 캐패시터에 연결되며, 삽입 전압 이득을 PSM1735를 사용하여 비교함으로써 임피던스의 공진 주파수를 더욱 유의미하게 만듭니다. 또한, 이중 와인딩 공통 모드 인덕터를 사용하여 EMI 필터를 구성하면 상대적으로 큰 캐패시터가 도입되지만, 인덕터 자체의 기생용량이 크게 제거된 것을 입증합니다. 또한, 이중 와인딩 3상 공통 모드 인덕터로 구성된 필터를 3상 인버터 회로에 배치하면 전통적인 3상 공통 모드 인덕터보다 더 나은 필터링 효과를 얻을 수 있습니다. 따라서 제안된 이중 와인딩 3상 공통 모드 인덕터는 특별한 감속 방법을 통해 인덕터의 용량에 미치는 영향을 줄일 수 있습니다.

Through-Silicon-via Inductor in Three-Dimensional Integrated Circuits: Modeling and Design for On-Chip Applications

Tida, Umamaheswara Rao ProQuest Dissertations & Theses University of Notr 2019 해외박사(DDOD)

This work focuses on the study of through-silicon-via (TSV) inductor and its utilization in various on-chip applications such as DC-DC converter and resonant clocking. TSVs are the critical enabling technology for three-dimensional integrated circuits (3D ICs). TSVs can be potentially used to implement inductors in 3-D integrated systems for a minimal footprint. However, di erent from conventional 2-D spiral inductors, TSV inductors are fully buried in the lossy substrate, thus su ering from low quality factor at high frequencies. On the other hand, a major limiting factor for the implementation of many on-chip circuits such as DC-DC converters and resonant clocking is the large area overhead induced by spiral inductors. Towards this, we propose to use TSV inductor instead of the spiral inductor to reduce the inductor area overhead.In this work, we rst systematically examine how various process and design parameters a ect the performance of TSV inductor. We then propose a novel shield mechanism utilizing the microchannel, a technique conventionally used for heat removal, to reduce the substrate losses at high frequencies. We also discuss on-chip magnetics based TSV inductor for high inductance density. We then demonstrate the e ectiveness of such TSV inductors in Inductive DC-DC converters. A single inductor multi-tier single voltage regulator design in 3D ICs with time-sharing and spatialsharing techniques is also proposed and is compared with the conventional design scheme. We then study the e ectiveness of TSV inductor in the resonant clocking scheme. Experimental results show that by replacing conventional spiral inductors with TSV inductors, inductor area reduced by up to 6.3x for on-chip applications.

RF IC에서 spiral inductors의 특성 해석 및 설계

홍성욱 成均館大學校 大學院 2003 국내석사

The demands placed on portable wireless communication equipment include low cost, low supply voltage, low power dissipation, low noise, high frequency of operation, and distortion. These design requirements cannot be met satisfactorily in many cases without the use of RF inductors. However, implementing the inductor on-chip has been regarded as an impractical task because of excessive parasitic coupling capacitance and substantial resistive losses due to metallization and the conductive silicon substrate. Hence, there is a great incentive to design, optimize, and models circular spiral inductors fabricated on Si substrate. Therefore, we analyzed a chip inductors using finite element method and established a set of design rules for circular spiral inductors.

(A) study on high performance CMOS VCOs

황과지 성균관대학교 일반대학원 2009 국내박사

A number of high performance CMOS VCOs/QVCOs are presented in this thesis. These VCOs/QVCOs are all detailedly analyzed and fabricated using advanced CMOS technologies. The measured results verify the new techniques proposed in this thesis. A self-switched biasing quadrature VCO is presented in this thesis. It is implemented by directly injecting the oscillation signals of one VCO core into the other VCO core through the divided tail current sources without additional active devices for coupling. The proposed coupling structure automatically switches the NMOS FETs used in VCO cores and current sources from strong inversion to accumulation. Since the deep switching of MOSFETs was reported to physically reduce flicker noise, the proposed QVCO is expected to improve the phase noise performance, which is confirmed experimentally. The designed QVCO using 0.18??m CMOS technology operates from 1.86 to 2.2 GHz with a 17% frequency tuning range. The measured phase noise is from -129.1 to -134.5 dBc/Hz at a 1 MHz offset, which is really close to ideal simulation results with the NMOS model disabling the flicker noise components. The average measured phase noise is 7.2 dB below the simulated one with a flicker noise model, which verifies the physical reduction of flicker noise by deep switching of MOSFET. The phase noise Figure-of-Merit (FoM) ranges from 179 to 185 over the entire tuning range. The QVCO dissipates 20mA from a 1.8V supply. This thesis also presents two oscillators, programmable wideband VCO and QVCO, which adopt modified gyrator-C type active inductors with PMOS transistors in the feedback path. New design equations for an active inductor considering the effects of the parasitic capacitance of PMOS are derived and used to design a high Q active inductor. The fabricated VCO and QVCO achieve frequency tuning ranges from 1.85 to 3.66 GHz and 1.55 to 3.61 GHz, respectively. The measured phase noise of VCO and QVCO range from -81.1 to -111.3 dBc/Hz and from -80.1 to -107.7 dBc/Hz at 3 MHz offset, respectively. Artificial dielectric is taken advantage to construct variable metal-to-metal capacitor and micro-strip line inductor (also named slab inductor) at millimeter-wave frequencies. These customized passive components are adopted to widen the frequency tuning range of the MMW VCOs. The MMW VCO adopts slap inductor with digitally controllable artificial dielectrics shows less effective in widening the frequency tuning range due to the neutralization in total parasitic capacitance caused by the coupling effect of the two differential inductor lines. This VCO shows a 700 MHz measured frequency range from 36.01 to 37.71 GHz. The measured phase noise at 3 MHz offset is from -97 to -100.7 dBc/Hz. Unlike the variable inductor, the variable metal-to-metal capacitor with digitally controllable artificial dielectrics shows large varying capacitance and high quality factor. The MMW VCO adopting this variable capacitor for sub band frequency tuning achieves a wide frequency tuning range. The measured operation frequency ranges from 43.5 to 45.5 GHz with 2 GHz tuning range while that of the VCO with MTM capacitor only ranges from 44.8 to 46 GHz. The measured phase noises at 3 MHz offset range from -97 to -102.7 dBc/Hz across the entire frequency band. Additionally, a 16-phase MMW VCO is also fabricated using 0.13 RF CMOS technology in this thesis. This multiple phase oscillator is composed of eight VCO cores. These eight VCO cores couple from one to another and finally make up a circle. The measured operation frequency ranges from 19.69 to 23.48 GHz with 19% tuning range. The measured phase noise at 1 MHz offset ranges from -91 to -98 dBc/Hz. Keywords: artificial dielectric, active inductor, CMOS, current source splitting, digitally controllable, flicker noise, gyrator-C, metal-to-metal capacitor, millimeter-wave, phase noise, programmable, quadrature VCO, self-switched biasing, transmission line inductor, variable, wideband, voltage controlled oscillator