1 "Ultra-Low Thermal Budget CMOS Process for 65 nm-node Low Operation-Power Applications" 647-650, 2002.
2 "The Inter-national Technology Roadmap for Semiconductor 2003" 2003
3 "Nanoscale CMOS" 87 (87): 537-570, 1999
4 "MOSFET Channel Length: Extraction and Interpretation" 47 (47): 160-170, 2000
5 "Impact of gate workfunction on device performance at the 50 nm technology node" 44 (44): 1077-1080,
6 "Impact of Lateral Source/Drain Abruptness on Device Performance" 49 no. 11 : -202, pp.1882-1890
7 "High-k dielectrics and MOSFET characteristics" 95-98, 2003
8 "Compatibility of dual metal gate electrodes with high-k dielectrics for CMOS" 323-326, 2003.
9 "ALD HfO2 using heavy water for improved MOSFET stability" 83-86, 2003.
10 "A Simulation Study to Evaluate the Feasibility of Midgap Workfunction Metal Gate in 25 nm Bulk CMOS" 24 (24): 707-709, 2003
1 "Ultra-Low Thermal Budget CMOS Process for 65 nm-node Low Operation-Power Applications" 647-650, 2002.
2 "The Inter-national Technology Roadmap for Semiconductor 2003" 2003
3 "Nanoscale CMOS" 87 (87): 537-570, 1999
4 "MOSFET Channel Length: Extraction and Interpretation" 47 (47): 160-170, 2000
5 "Impact of gate workfunction on device performance at the 50 nm technology node" 44 (44): 1077-1080,
6 "Impact of Lateral Source/Drain Abruptness on Device Performance" 49 no. 11 : -202, pp.1882-1890
7 "High-k dielectrics and MOSFET characteristics" 95-98, 2003
8 "Compatibility of dual metal gate electrodes with high-k dielectrics for CMOS" 323-326, 2003.
9 "ALD HfO2 using heavy water for improved MOSFET stability" 83-86, 2003.
10 "A Simulation Study to Evaluate the Feasibility of Midgap Workfunction Metal Gate in 25 nm Bulk CMOS" 24 (24): 707-709, 2003
11 "50 nm gate length technology with 9-layer Cu interconnects for 90 nm node SoC applications" 69-72, 2002.