1 E. J. Marinissen, "http://www. hitech-projects.com/itc02socbenchm"
2 E. J. Marinissen, "http://www. hitech-projects.com/itc02socbenchm"
3 Y. Xia, "Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints" 100-105, Nov.2003
4 E. Cota, "The Impact of NoC Reuse on the Testing of Core-based Systems" 128-133, April2003.
5 C. Liu, "Test Scheduling for Network-on-Chip with BIST and Precedence Constraints" 1369-1378, Oct.2004.
6 K. Chakrabarty, "Test Scheduling for Core-Based Systems Using Mixed-Integer Linear Programming" 1163-1174, Oct.2000.
7 W. Zou, "SOC Test Scheduling Using Simulated Annealing" 325-330, April2003.
8 A. M. Amory, "Reducing Test Time with Processor Reuse in Network-on-Chip Based System" the 17th Symposium on Integrated Circuits and Systems Design 111-116, Sep.2004.
9 J. Im, "RAIN(RAndom INsertion) Scheduling Algorithm for SoC Test" 242-247, Nov.2004.
10 C. Liu, "Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking" 349-354, May2005.
1 E. J. Marinissen, "http://www. hitech-projects.com/itc02socbenchm"
2 E. J. Marinissen, "http://www. hitech-projects.com/itc02socbenchm"
3 Y. Xia, "Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints" 100-105, Nov.2003
4 E. Cota, "The Impact of NoC Reuse on the Testing of Core-based Systems" 128-133, April2003.
5 C. Liu, "Test Scheduling for Network-on-Chip with BIST and Precedence Constraints" 1369-1378, Oct.2004.
6 K. Chakrabarty, "Test Scheduling for Core-Based Systems Using Mixed-Integer Linear Programming" 1163-1174, Oct.2000.
7 W. Zou, "SOC Test Scheduling Using Simulated Annealing" 325-330, April2003.
8 A. M. Amory, "Reducing Test Time with Processor Reuse in Network-on-Chip Based System" the 17th Symposium on Integrated Circuits and Systems Design 111-116, Sep.2004.
9 J. Im, "RAIN(RAndom INsertion) Scheduling Algorithm for SoC Test" 242-247, Nov.2004.
10 C. Liu, "Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking" 349-354, May2005.
11 E. Cota, "Power-Aware NoC Reuse on the Testing of Core-Based Systems" 1 : 612-621, Sep.2003.
12 V. Iyengar, "On using Rectangle Packing for SOC Wrapper/TAM Co-Optimization" 253-258, 2002.
13 L. Benini, "Networks on Chips: A New SoC Paradigm" 35 : 70-78, Jan.2002.
14 M. Nahvi, "Indirect Test Architecture for SoC Testing" 23 (23): 1128-1142, July2004.
15 A. Sehgal, "Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures" 422-427, Feb.2004.
16 B. Vermeulen, "Bringing Communication Networks on a Chip: Test and Verification Implications" 41 : 74-81, Sep.2003
17 E. Larsson, "A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling" 1135-1144, Sep.2003.
18 E. Larsson, "A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling" 1135-1144, Sep.2003.
19 J. Ahn, "A Practical Test Scheduling using Network-Based TAM in Network on Chip Architecture" LNCS 3740 : 614-624, Oct.2005.
20 P. Guerrier, "A Generic Architecture for On-Chip Packet-Switched Interconnections" 250-256, Mar.2000.