Design of High-Performance Intra Prediction Circuit for H.264 Video Decoder

다국어 초록 (Multilingual Abstract)

This paper proposes a high-performance architecture of the H.264 intra prediction circuit. The proposed architecture uses the 4-input and 2-input common computation units and common registers for fast and efficient prediction operations. It avoids excessive power consumption by the efficient control of the external and internal memories. The implemented circuit based on the proposed architecture can process more than 60 HD (1,920x1,088) image frames per second at the maximum operating frequency of 101 ㎒ by using 130 nm standard cell library.

목차 (Table of Contents)

• Abstract
• Ⅰ. INTRODUCTION
• Ⅱ. PROPOSED ARCHITECTURE
• Ⅲ. EXPERIMENTAL RESULTS
• Ⅳ. CONCLUSIONS
• ACKNOWLEDGMENTS
• REFERENCES

참고문헌 (Reference)

1 심재오, "공통연산부를 공유하는 H.264 디코더용 인트라 예측 회로 설계" 대한전자공학회 45 (45): 103-109, 2008

2 T-C. Chen, "Hardware Architecture Design of an H.264/AVC Video Codec" 750-757, 2006

3 박종식, "H.264 복호기에서 움직임 보상기와 연계하여메모리 접근면에서 효율적인 인트라 예측기 설계" 대한전자공학회 45 (45): 37-42, 2008

4 이찬호, "H.264 복호기를 위한 스케일러블 인트라 예측기 구조 설계" 대한전자공학회 45 (45): 77-82, 2008

5 "Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264/ISO/IEC 14496-10 AVC)"

6 W. T. Staehler, "Architecture of an HDTV Intraframe Predictor for a H.264 Decoder" 229-233, 2006