A Scaling Trend of Variation-Tolerant SRAM Circuit Design in Deeper Nanometer Era

다국어 초록 (Multilingual Abstract)

Evaluation results about area scaling capabilities of various SRAM margin-assist techniques for random VT variability issues are described. Various efforts to address these issues by not only the cell topology changes from 6T to 8T and 10T but also incorporating multiple voltage-supply for the cell terminal biasing and timing sequence controls of read and write are comprehensively compared in light of an impact on the required area overhead for each design solution given by ever increasing VT variation (σVT). Two different scenarios which hinge upon the EOT (Effective Oxide Thickness) scaling trend of being pessimistic and optimistic, are assumed to compare the area scaling trends among various SRAM solutions for 32 ㎚ process node and beyond. As a result, it has been shown that 6T SRAM will be allowed long reign even in 15 ㎚ node if σVT can be suppressed to ＜ 70 ㎷ thanks to EOT scaling for LSTP (Low Standby Power) process.

목차 (Table of Contents)

• Abstract
• Ⅰ. INTRODUCTION
• Ⅱ. CELL STABILITY IMPROVEMENT AND ITS LIMITATION
• Ⅲ. NEW CELL TOPOLOGY AND ITS IMPACT
• Ⅳ. READ AND WRITE MULTIPLEXING AND ITS IMPACT
• Ⅴ. ECC SCHEME FOR REDUNDANCY
• Ⅵ. AREA SCALING TREND COMPARISONS
• Ⅶ. CONCLUSIONS
• ACKNOWLEDGMENTS
• REFERENCES

참고문헌 (Reference)

1 R. Kanj, "importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events" 69-72, 2006

2 K. Takeuchi, "Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies" 467-470, 2007

3 L. Chang, "Stable SRAM Cell Design for the 32 nm Node and Beyond" 128-129, 2005

4 G. Tsutui, "Reduction of Vth variation by work fuction optimization for 45-nm node SRAM cell" 158-159, 2008

5 K.J.Kuhn, "Reducing Variation in Advanced Logic Technologies:Approaches to Process and Design for Manufacturability of Nanoscale CMOS" 471-474, 2007

6 A. Asenov, "Origin of the Asymmetry in the Magnitude of the Statistical Variability of n- and p-Channel Poly-Si Gate Bulk MOSFETs" 29 (29): 913-915, 2008

7 M. Saibal, "Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS" 2005

8 M. Pelgrom, "Matching properties of MOS transistors" 24 (24): 1433-1439, 1989

9 K. Itoh, "Low-Voltage Limitations of Memory-Rich Nano-Scale CMOS LSIs" 11-13, 2007

10 M.Suzuki, "Lanthanum Aluminate Gate Dielectric Technology with Direct Interface" 62 (62): 37-41, 2007

11 "International Technology Roadmap for Semiconductors 2007"

12 T. S. Doorn, "Importance sampling Monte Carlo simulations for accurate estimation of SRAM yield" 230-233, 2008

13 J. Pille, "Implementation of the CELL Broadband Engine in a 65 nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6 GHz at 1.3 V" 322-323, 2007

14 H.Yamauchi, "Embedded SRAM trend in nanoscale CMOS" 19-22, 2007

15 H.Yamauchi, "Embedded SRAM circuit design technologies for a 45 nm and beyond" 1028-1033, 2007

16 S.J.Lee, "Characteristics of TaN gate MOSFET with ultrathin hafnium oxide" 39-42, 2000

17 T. Tsunomura, "Analyses of 5σ Vth Fluctuation in 65 nm MOSFETs using Takeuchi plot" 156-157, 2008

18 H. Pilo, "An SRAM Design in 65 nm and 45 nm Technology Nodes Featuring Read and Write- Assist Circuits to Expand Operating Voltage" 15-16, 2006

19 정연배, "An Experimental 0.8 V 256-kbit SRAM Macro with Boosted Cell Array Scheme" 한국전자통신연구원 29 (29): 457-462, 2007

20 Y. Morita, "An Area- Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment" 256-257, 2007

21 L. Chang, "An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches" 43 (43): 956-963, 2008

22 E. P. Gusev, "Advanced high-j dielectric stacks with polySi and metal gates:Recent progress and current challenges" 50 (50): 387-410, 2006

23 V. Ramadurai, "A Disturb Decoupled Column Select 8T SRAM Cell" 25-28, 2007

24 X. Chen, "A Cost Effective 32 nm High-K/ Metal Gate CMOS Technology for Low Power Applications with Single-Metal/Gate-First Process" 88-89, 2008

25 S. Ohbayashi, "A 65 nm Soc Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits" 17-18, 2006

26 V. Naveen, "A 65 nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy" 328-329, 2007

27 L. Chang, "A 5.3 GHz 8T-SRAM with Operation Down to 0.41 V in 65 nm CMOS" 252-253, 2007

28 H. Pilo, "A 450ps Access-Time SRAM Macro in 45 nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management" 378-379, 2008

29 M. Yabuuchi, "A 45 nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations" 326-327, 2007

30 D. P. Wang, "A 45 nm Dual-Port SRAM with Write and Read Capability Enhancement at Low Voltage" 211-214, 2007

31 I-J. Chang, "A 32 kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90 nm CMOS" 388-622, 2008

32 K. Zhang, "A 3 GHz 70 Mb SRAM in 65 nm CMOS Technology with Integrated Column-Based Dynamic Power Supply" 31 (31): 474-611, 2006

33 F. Hamzaoglu, "A 153Mb SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45 nm Hi-K Metal Gate CMOS Technology" 376-377, 2008

34 Y. Wang, "A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications" 324-325, 2007

35 H. Yamauchi, "A 0.8 V/100 MHz/sub-5 mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) scheme" 126-127, 1996

36 Y. H. Chen, "A 0.6 V 45 nm Adaptive Dualrail SRAM Compiler Circuit Design for Lower VDD_min VLSIs" 210-211, 2008

37 M. Yamaoka, "65 nm Low-Power High-Density SRAM Operable at 1.0 V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS" 384-385, 2008

38 S. Ekbote, "45 nm low-power CMOS SoC technology with aggressive reduction of random variation for SRAM and analog transistor" 158-159, 2008