Virtual Junction Temperature Estimation during Dynamic Power Cycling Tests

다국어 초록 (Multilingual Abstract)

This work proposes an acquisition concept, allowing measurement of the virtual junction temperature during application-oriented active power cycling tests (PCTs). PCTs are conceptualized with the failure mechanisms of conventional Si-based devices in mind, however, wide-bandgap devices can exhibit parameter inconsistencies like the dynamic ON-state resistance in GaN or the bias temperature instability in SiC. Application-oriented, dynamic active power cycling tests promise more accurate results than conventional quasi-static DC tests, but consistency with conventional accelerated aging tests is difficult to keep, as different parameter acquisition methods must be used. The combination of a novel high-voltage protected current source with a switch node blocking stage enables temperature estimation via the conventional reverse-blocking voltage method to alleviate this challenge. The proposed testbench achieves a time delay in the measurement of the virtual junction temperature of 120 μs in the dynamic PCT of a SiC power MOSFET module.

목차 (Table of Contents)

• Abstract
• I. Introduction
• II. Topologies for Power Cycling Tests
• III. Approach and Method
• IV. Setup and Results
• V. Conclusion
• References