Investigation of Line-edge Roughness Effects on Electrical Characteristics of Nanowire Tunnel FETs and MOSFETs

다국어 초록 (Multilingual Abstract)

In this paper, the influences of design parameters on the line-edge roughness (LER) effects in a nanowire tunnel field-effect transistor (TFET) and a metal-oxide-semiconductor FET (MOSFET) have been discussed with the help of technology computer-aided design simulation. The strength of LER effects are quantitatively examined by correlation coefficients (R) between electrical performances and variations of nanowire dimensions; 1) threshold voltage (Vth) vs. channel volume, 2) ON-state current (ION) vs. channel volume, 3) Vth vs. source-channel junction area, and 4) ION vs. source-channel junction area. According to the simulation results, the nanowire MOSFET shows the similar values from 0.47-R to 0.74-R for all cases. On the other hand, the nanowire TFET only depends on the variation in the source-channel junction area with R more than 0.4.

참고문헌 (Reference)

1 W. Y. Choi, "Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec" 28 (28): 743-745, 2007

2 H. W. Kim, "Tunneling field-effect transistor with Si/SiGe material for high current drivability" 53 (53): 06JE12-06JE12-4, 2014

3 E. O. Kane, "Theory of tunneling" 32 (32): 83-91, 1961

4 F. Conzatti, "Strain-induced performance improvements in InAs nanowire tunnel FETs" 59 (59): 2085-2092, 2012

5 K. Tomioka, "Steepslope tunnel field-effect transistors using III-V nanowire/Si heterojunction" 47-48, 2012

6 X. Wang, "Statistical variability and reliability in nanoscale FinFETs" 5.4.1-5.4.4, 2011

7 Synopsys Inc, "Sentaurus Device User Guide -v.K-2015.06"

8 T. Sakurai, "Perspectives of low-power VLSI’s" E87-C (E87-C): 429-436, 2004

9 E. J. Nowak, "Maintaining the benefits of CMOS scaling when scaling bogs down" 46 (46): 169-180, 2002

10 A. Asenov, "Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness" 50 (50): 1254-1260, 2003

11 W. Y. Choi, "Influence of line-edge roughness on multiple-gate tunnel field-effect transistors" 56 (56): 04CD06-, 2017

12 K. E. Moselund, "InAs-Si nanowire heterojunction tunnel FETs" 33 (33): 1453-1455, 2012

13 C. Chen, "Impacts of work function variation and line-edge roughness on TFET and FinFET devices and logic circuits" 1-2, 2014

14 E. Baravelli, "Impact of lineedge roughness on FinFET matching performance" 54 (54): 2466-2474, 2007

15 N. Damrongplasit, "Impact of gate line-edge roughness (LER)versus random dopant fluctuations (RDF) on germanium-source tunnel FET performance" 12 (12): 1061-1067, 2013

16 E. Baravelli, "Impact of LER and random dopant fluctuations on FinFET matching performance" 7 (7): 291-298, 2008

17 S. W. Kim, "Hump Effects of Germanium/Silicon Heterojunction Tunnel Field-Effect Transistors" 63 (63): 2583-2588, 2016

18 M. Kim, "High Ion/Ioff Ge-source ultrathin body strained-SOI tunnel FETs" 1 (1): 13.2.1-13.2.4, 2014

19 K. Patel, "Gate line edge roughness model for estimation of FinFET performance variability" 56 (56): 3055-3063, 2009

20 A. Mishra, "Double gate vertical tunnel FET for hybrid CMOS-TFET based low standby power logic circuits" 1-4, 2013

21 Z. X. Chen, "Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires" 30 (30): 754-756, 2009

22 S. W. Kim, "Demonstration of L-Shaped Tunnel Field-Effect Transistors" 63 (63): 1774-1778, 2016

23 K. Terada, "Comparison of MOSFET-threshold-voltage extraction methods" 45 (45): 35-40, 2001

24 Y. H. Cheng, "Comparison of MOSFET threshold voltage extraction methods with temperature variation" 126-131, 2019

25 Seunggyu Ji, "Characteristics of Recess Structure Tunneling Field Effect Transistor for High on Current Drivability" 대한전자공학회 18 (18): 360-366, 2018

26 P. Y. Wang, "Band engineering to improve average subthreshold swing by suppressing low electric field band-to-band tunneling with epitaxial tunnel layer tunnel FET structure" 15 (15): 74-79, 2016

27 S. Cristoloveanu, "A review of sharp-switching devices for ultra-low power applications" 2016