저전력 BFSK 수신기의 FPGA 구현 = FPGA Implementation of a Low Power BFSK Receiver

다국어 초록 (Multilingual Abstract)

This paper is to implement a low power Frequency Shift Keying(FSK) receiver using xilinx System Generator. The receiver incorporates a 16 point Fast Fourier Transform(FFT) for symbol detection. The design units of the receiver are digital designs for better efficiency and reliability. The receiver functions on one bit data processing and supports data rates 10kbps. In addition CORDIC algorithm is used for avoiding complex multiplications while computing FFT, multiplication of twiddle factor is substituted by rotators. The design and simulation of the receiver is carried out in Simulink, then the simulink model is translated to a hardware model to implement FPGA using Xilinx System Generator and to verify performance.

목차 (Table of Contents)

• Ⅰ. 서론 1
• Ⅱ. FSK 2
• Ⅲ. FFT 기반 검출기 2
• Ⅳ. CORDIC 2
• Ⅴ. CORDIC 3
• Ⅵ. 검출과정 3
• Ⅶ. Simulink 모델 4
• 1. Simulink 모델의 동작 4
• 2. 시뮬레이션 결과 4
• 3. 도플러 천이에 대한 수신기 성능 5
• 4. 수신기 BER 성능 6
• 5. A/D 클럭 변화에 대한 수신기 성능 5
• Ⅷ. 수신기의 System Generator 모델 구현 6
• 1. System Generator 설계 모델 6
• 2. Xilinx Model Down conversion 7
• 3. Xilinx Model : FFT 검출기 7
• 4. 시뮬레이션 결과 7
• 5. Xilinx FPGA로의 합성 7
• Ⅸ. 결론 및 향후 계획 7