RISS 학술연구정보서비스

검색
다국어 입력

http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.

변환된 중국어를 복사하여 사용하시면 됩니다.

예시)
  • 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
  • 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
닫기
    인기검색어 순위 펼치기

    RISS 인기검색어

      Reliability Characterization in consideration of Self-Heating in FinFET Technology

      한글로보기

      https://www.riss.kr/link?id=T14741778

      • 0

        상세조회
      • 0

        다운로드
      서지정보 열기
      • 내보내기
      • 내책장담기
      • 공유하기
      • 오류접수

      부가정보

      다국어 초록 (Multilingual Abstract)

      With technology node scaling, fin shape (3D) engineering enables higher performance for the smaller fin pitch and reducing footprint. Generally, FinFETs have been engineered to be taller and narrower for better electrostatics and performance at lower VT operation. The taller the fin height and the narrower the fin bottom width allows more difficult to remove the heat generated at the top of the fin. It is discussed that the self-heating only matters during device operation and mainly affects hot carrier injection (HCI) aging from device perspective, more severe in PFETs than in NFETs due to higher Ea. Increase of fin self-heating effect and potential reliability issues must be well understood, characterized, and modeled for design of products. By characterizing the duty in AC operation, fin self-heating on high speed logic could be mitigated or can be built into the design by embedding self-heating model into SPICE simulation along with aging run. Self-heating effect have not been very apparent on the Ring Oscillators with their very high frequency operation and voltages around 1/2xVdd during switching transitions even for long durations (of several hundred hours of stress). Any digital logic circuits that operate on the giga-hertz (GHz)-level with very low duty would most practically experience little fin self-heating impacts. As circuits do continue to operate longer, there can be residual impact of self-heating effect that gets accumulated as time elapses. Therefore, those effects must be carefully taken into account in design by running various duty scenarios. On analog devices and circuits that have more static bias and higher duty cycles, typically longer channel devices are used to minimize the process variations. A careful reliability characterization in consideration of self-heating effect is needed as fin dimension continues to scale very aggressively.
      번역하기

      With technology node scaling, fin shape (3D) engineering enables higher performance for the smaller fin pitch and reducing footprint. Generally, FinFETs have been engineered to be taller and narrower for better electrostatics and performance at lower ...

      With technology node scaling, fin shape (3D) engineering enables higher performance for the smaller fin pitch and reducing footprint. Generally, FinFETs have been engineered to be taller and narrower for better electrostatics and performance at lower VT operation. The taller the fin height and the narrower the fin bottom width allows more difficult to remove the heat generated at the top of the fin. It is discussed that the self-heating only matters during device operation and mainly affects hot carrier injection (HCI) aging from device perspective, more severe in PFETs than in NFETs due to higher Ea. Increase of fin self-heating effect and potential reliability issues must be well understood, characterized, and modeled for design of products. By characterizing the duty in AC operation, fin self-heating on high speed logic could be mitigated or can be built into the design by embedding self-heating model into SPICE simulation along with aging run. Self-heating effect have not been very apparent on the Ring Oscillators with their very high frequency operation and voltages around 1/2xVdd during switching transitions even for long durations (of several hundred hours of stress). Any digital logic circuits that operate on the giga-hertz (GHz)-level with very low duty would most practically experience little fin self-heating impacts. As circuits do continue to operate longer, there can be residual impact of self-heating effect that gets accumulated as time elapses. Therefore, those effects must be carefully taken into account in design by running various duty scenarios. On analog devices and circuits that have more static bias and higher duty cycles, typically longer channel devices are used to minimize the process variations. A careful reliability characterization in consideration of self-heating effect is needed as fin dimension continues to scale very aggressively.

      더보기

      목차 (Table of Contents)

      • 1. Introduction 1
      • 2. Experimetal work 3
      • 2.1 FinFET Technology Scaling 3
      • 2.2 Characterization Methods in advanced FinFETs 6
      • 2.2.1 Hot Carrier Injection 6
      • 1. Introduction 1
      • 2. Experimetal work 3
      • 2.1 FinFET Technology Scaling 3
      • 2.2 Characterization Methods in advanced FinFETs 6
      • 2.2.1 Hot Carrier Injection 6
      • 2.2.2 Self-Heating Effect 7
      • 2.2.3 Ring Oscillator Aging 11
      • 3. Self-heating Effect in FinFET Reliability 13
      • 3.1 Hot Carrier Analysis in FinFET 13
      • 3.2 Self-heating Effect in FinFET 15
      • 3.3 New methodology to decouple SHE from HCI 17
      • 3.4 Self-heating driven drain-biased TDDB 24
      • 4. HCI Effect in FinFET Ring Oscillator 30
      • 4.1 Ring Oscillator Degradation 30
      • 4.2 New RO structures to decouple BTI from HCI 31
      • 4.3 HCI Duty Cycle in RO 35
      • 5. Conclusion 38
      • Reference 39
      • Korean Abstract 42
      더보기

      분석정보

      View

      상세정보조회

      0

      Usage

      원문다운로드

      0

      대출신청

      0

      복사신청

      0

      EDDS신청

      0

      동일 주제 내 활용도 TOP

      더보기

      주제

      연도별 연구동향

      연도별 활용동향

      연관논문

      연구자 네트워크맵

      공동연구자 (7)

      유사연구자 (20) 활용도상위20명

      이 자료와 함께 이용한 RISS 자료

      나만을 위한 추천자료

      해외이동버튼